M93C66-WMN6TP/S ,4 Kbit (8-bit or 16-bit wide) MICROWIRE serial access EEPROMfeatures . . 93.1 Supply voltage (V ) . 9CC3.1.1 Operating supply voltage (V ) 9CC3 ..
M93C76-MN3 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMLogic Diagram . . 4Table 2. Signal Names . . 4Table 3. Memory Size versus Organizatio ..
M93C76MN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMFEATURES SUMMARY . . . . . 1Table 1. Product List . . . . 1Figure 1. Packages . ..
M93C76-MN6T ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMAbsolute Maximum Ratings . . . . . . . 12DC AND AC PARAMETERS . 13Table 9. Operating Cond ..
M93C76-WMN6T ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMM93C86, M93C76, M93C66M93C56, M93C4616Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)MIC ..
M93C76-WMN6TP ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMLogic Diagram . . 4Table 2. Signal Names . . 4Table 3. Memory Size versus Organizatio ..
MAX172BCWG+ ,Complete 10µs CMOS 12-Bit ADC19-0437; Rev f,' 2/91
lVl/J X I/Vl
Complete 10,us CMOS 12-Bit ADC
MAX172BENG+ ,Complete 10µs CMOS 12-Bit ADCFeatures
. 12-Bit Resolution and Linearity
. 10ps Conversion Time
. No Missing Codes
. On-Chip ..
MAX172BEWG+ ,Complete 10µs CMOS 12-Bit ADCApplications
Digital Signal Processing (DSP)
High Accuracy Process Control
High Speed Data Acq ..
MAX1733EUK ,Low-Voltage / Step-Down DC-DC Converters in SOT23ELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V, SHDN = IN, T = 0°C to +85°C. Typical values are at T ..
MAX1733EUK+T ,Low-Voltage, Step-Down DC-DC Converters in SOT23ELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V, SHDN = IN, T = 0°C to +85°C. Typical values are at T ..
MAX1733EUK-T ,Low-Voltage / Step-Down DC-DC Converters in SOT23ApplicationsGuide, then insert the proper designator into the blanks above tocomplete the part numb ..
M93C56-RMN6TP-M93C66-WMN6TP/S
2 Kbit (8-bit or 16-bit wide) MICROWIRE serial access EEPROM
November 2013 DocID4997 Rev 15 1/33
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE serial access EEPROM
Datasheet - production data
Features Industry standard MICROWIRE bus Single supply voltage: 2.5 V to 5.5 V for M93Cx6-W 1.8 V to 5.5 V for M93Cx6-R Dual organization: by word (x16) or byte (x8) Programming instructions that work on: byte,
word or entire memory Self-timed programming cycle with auto-erase:
5 ms READY/BUSY signal during programming 2 MHz clock rate Sequential read operation Enhanced ESD/latch-up behavior More than 4 million write cycles More than 200-year data retention Packages SO8, TSSOP8, UFDFPN8 packages:
RoHS-compliant and Halogen-free
(ECOPACK®) PDIP8 package:
RoHS-compliant (ECOPACK1®)
Table 1. Device summary
Contents M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x2/33 DocID4997 Rev 15
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.3 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.4 Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.5 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID4997 Rev 15 3/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of tables M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x4/33 DocID4997 Rev 15
List of tablesTable 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. DC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. DC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. AC characteristics (M93Cx6-W, M93Cx6-R, device grade 6). . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. AC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. UFDFPN8 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 29
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID4997 Rev 15 5/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x List of figures
List of figuresFigure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. M93Cx6 ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. READ, WRITE, WEN, WDS sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. UFDFPN8 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 29
Description M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x6/33 DocID4997 Rev 15
1 DescriptionThe M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed
through the MICROWIRE bus protocol. The memory array can be configured either in bytes
(x8b) or in words (x16b).
The M93Cx6-W devices operate within a voltage supply range from 2.5 V to 5.5 V and the
M93Cx6-R devices operate within a voltage supply range from 1.8 V to 5.5 V. All these
devices operate with a clock frequency of 2 MHz (or less), over an ambient temperature
range of -40 °C / +85 °C.
Figure 1. Logic diagram
Table 2. Memory size versus organization
Table 3. Signal names
DocID4997 Rev 15 7/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x Description See Section 11: Package mechanical data for package dimensions, and how to identify pin-1. DU = Don’t Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or VSS.
Connecting to the serial bus M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x Connecting to the serial busFigure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the tSLCH requirement is met. The typical value of R is 100 k.
Figure 3. Bus master and memory devices on the serial bus
DocID4997 Rev 15 9/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x Operating features
3 Operating features
3.1 Supply voltage (V CC)
3.1.1 Operating supply voltage (VCC)Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable
DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor
(usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
3.1.2 Power-up conditionsWhen the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float and should be driven to VSS, it is therefore
recommended to connect the S line to VSS via a suitable pull-down resistor.
The VCC rise time must not vary faster than 1 V/µs.
3.1.3 Power-up and device resetIn order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Operating conditions, in
Section 10: DC and AC parameters).
When VCC passes the POR threshold, the device is reset and is in the following state: Standby Power mode deselected (assuming that there is a pull-down resistor on the S line)
3.1.4 Power-downAt power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in the Standby Power mode (that is,
there should be no internal Write cycle in progress).
Memory organization M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x10/33 DocID4997 Rev 15
4 Memory organizationThe M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization
Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected;
when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is
selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set
either to VSS or VCC to reach the device minimum power consumption (as any voltage
between VSS and VCC applied to ORG input may increase the device Standby current).
Figure 4. M93Cx6 ORG input connection
DocID4997 Rev 15 11/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x Instructions
5 InstructionsThe instruction set of the M93Cx6 devices contains seven instructions, as summarized in
Table 4 to Table 6. Each instruction consists of the following parts, as shown in Figure 5:
READ, WRITE, WEN, WDS sequences: Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock
(C) being held low. A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of
Serial Clock (C). Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the op-code). The address bits of the byte or word that is to be accessed. For the M93C46, the
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 4). For the M93C56 and M93C66, the address is made up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8
organization (see Table 6).
The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as
slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC
characteristics” tables, in Section 10: DC and AC parameters.
Table 4. Instruction set for the M93C46 X = Don't Care bit.
Instructions M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x12/33 DocID4997 Rev 15
Table 5. Instruction set for the M93C56 and M93C66 X = Don't Care bit. Address bit A8 is not decoded by the M93C56. Address bit A7 is not decoded by the M93C56.
Table 6. Instruction set for the M93C76 and M93C86 X = Don't Care bit. Address bit A10 is not decoded by the M93C76. Address bit A9 is not decoded by the M93C76.
DocID4997 Rev 15 13/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x Instructions
5.1 Read Data from MemoryThe Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the
internal address register and clocks out the next byte (or word) as long as the Chip Select
Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)
and a continuous stream of data can be read (the address counter automatically rolls over to
00h when the highest address is reached).
5.2 Erase and Write data
5.2.1 Write Enable and Write DisableThe Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After a
Write Enable (WEN) instruction has been executed, erasing and writing remains enabled
until a Write Disable (WDS) instruction is executed, or until VCC falls below the power-on
reset threshold voltage. To protect the memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read
Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write
Disable (WDS) instructions.
5.2.2 WriteFor the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write
cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an
explicit erase instruction before a Write Data to Memory (WRITE) instruction.
Instructions M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x14/33 DocID4997 Rev 15
Figure 5. READ, WRITE, WEN, WDS sequences For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table 6.
DocID4997 Rev 15 15/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x Instructions
5.2.3 Write AllAs with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with
same Data (WRAL) instruction requires that a dummy address be provided. As with the
Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.
This value is written to all the addresses of the memory device. The completion of the cycle
can be detected by monitoring the READY/BUSY line, as described next.
Figure 6. WRAL sequence For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6.
Instructions M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x16/33 DocID4997 Rev 15
5.2.4 Erase Byte or WordThe Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Figure 7. ERASE, ERAL sequences For the meanings of An and Xn, please see Table 4, Table 5 and Table 6.
5.2.5 Erase AllThe Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.
DocID4997 Rev 15 17/33
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x READY/BUSY status
6 READY/BUSY statusWhile the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of tSLSH, before this status information
becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write
cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6 is ready to receive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.
Initial delivery stateThe device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
