M93C46-WMN3TP/S ,Automotive 1 Kbit MICROWIRE serial access EEPROMAbsolute maximum ratings . 20Table 8. Operating conditions (M93Cx6) . . . . . 21Table 9. ..
M93C46WMN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMFEATURES SUMMARY Industry Standard MICROWIRE Bus Figure 1. Packages Single Supply Voltage:– 4.5 t ..
M93C46-WMN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMLogic Diagram . . 4Table 2. Signal Names . . 4Table 3. Memory Size versus Organizatio ..
M93C46-WMN6P ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMFEATURES SUMMARY . . . . . 1Table 1. Product List . . . . 1Figure 1. Packages . ..
M93C46-WMN6T ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMFEATURES SUMMARY Industry Standard MICROWIRE Bus Figure 1. Packages Single Supply Voltage:– 4.5 t ..
M93C46-WMN6TP ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMM93C86, M93C76, M93C66M93C56, M93C4616Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)MIC ..
MAX1718 ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)Applicationsresponse to load transients while maintaining a relatively♦ 2V to 28V Battery Input Ran ..
MAX1718BEEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIApplicationsD3 DLD4GNDIMVP-II™ Notebook ComputersZMODEMUX CONTROL2-Cell to 4-Cell Li+ Battery to CP ..
MAX1718BEEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIFeatures Quick-PWM Architecture The MAX1718 step-down controller is intended for coreCPU DC-DC co ..
MAX1718B-EEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIApplicationsD3 DLD4GNDIMVP-II™ Notebook ComputersZMODEMUX CONTROL2-Cell to 4-Cell Li+ Battery to CP ..
MAX1718BEEI+ ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)Applicationsresponse to load transients while maintaining a relatively♦ 2V to 28V Battery Input Ran ..
MAX1718BEEI-T ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)Features♦ Quick-PWM Architecture The MAX1718 step-down controller is intended for coreCPU DC-DC co ..
M93C46-WMN3TP/S-M93C86-WMN3TP/S
Automotive 1 Kbit MICROWIRE serial access EEPROM
March 2012 Doc ID 022572 Rev 1 1/32
M93C86-125 M93C76-125 M93C66-125
M93C56-125 M93C46-125Automotive 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE serial EEPROM
Datasheet − production data
Features Industry standard MICROWIRETM bus Memory array: 1 Kb, 2Kb, 4Kb, 8 Kb or 16 Kb Dual organization: by word (x16) or byte (x8) Write Byte within 5 ms Word within 5 ms READY/BUSY signal during programming 2 MHz clock rate Sequential read operation Single supply voltage: 4.5 V to 5.5 V or 2.5 V
to 5.5 V Operating temperature range: -40°c up to
125°C Enhanced ESD protection More than 1 million Write cycles More than 40-year data retention Packages SO8, TSSOP8 packages: RoHS-compliant
and Halogen-free (ECOPACK2®) PDIP8 package: RoHS-compliant
(ECOPACK1®)
Contents M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-1252/32 Doc ID 022572 Rev 1
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Contents
Doc ID 022572 Rev 1 3/32
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of tables M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125
4/32 Doc ID 022572 Rev 1
List of tables
Table 1. Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Instruction set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Operating conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. AC measurement conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. AC measurement conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. DC characteristics (M93Cx6, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. DC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. AC characteristics (M93Cx6, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. AC characteristics (M93Cx6-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 28
Table 19. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 29
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 List of figures
Doc ID 022572 Rev 1 5/32
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. DIP, SO and TSSOP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. READ, WRITE, WEN, WDS sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. AC testing input output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. Synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Synchronous timing (Read or Write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 28
Figure 14. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 29
Description M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125
6/32 Doc ID 022572 Rev 1
1 Description
The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed
through the MICROWIRE bus protocol. The memory array can be configured either in bytes
(x8b) or in words (x16b).
The M93Cx6 devices operate within a voltage supply range from 4.5 V to 5.5 V, and the
M93Cx6-W devices operate within a voltage supply range from 2.5 V to 5.5 V.
The M93Cx6 devices are guaranteed over the -40°C/+125°C temperature range and are
compliant with the Automotive standard AEC-Q100 Grade1.
Figure 1. Logic diagram
Table 1. Memory size versus organization
M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Description
Doc ID 022572 Rev 1 7/32
The M93Cx6 is accessed by a set of instructions, as summarized in Table 3, and in more
detail in Table 4: Instruction set for the M93C46 to Table 6: Instruction set for the M93C76
and M93C86).
A Read Data from Memory (READ) instruction loads the address of the first byte or word to
be read in an internal address register. The data at this address is then clocked out serially.
The address register is automatically incremented after the data is output and, if Chip Select
Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In
this way, the memory can be read as a data stream from eight to 16384 bits long (in the
case of the M93C86), or continuously (the address counter automatically rolls over to 00h
when the highest address is reached).
Programming is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an Erase cycle
prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the
byte or word locations of the M93Cx6. After the start of the programming cycle, a
Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is
driven High.
An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when
the supply is too low.
Table 2. Signal names
Table 3. Instruction set for the M93Cx6
Description M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125
8/32 Doc ID 022572 Rev 1
Figure 2. DIP, SO and TSSOP connections (top view) See Section 12: Package mechanical data for package dimensions, and how to identify pin-1. DU = Don’t Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to VCC or VSS.
M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Connecting to the serial bus 9/32 Connecting to the serial bus
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the tSLCH requirement is met. The typical value of R is 100 kΩ.
Figure 3. Bus master and memory devices on the serial bus
Operating features M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125
10/32 Doc ID 022572 Rev 1
3 Operating features
3.1 Supply voltage (V CC)
3.1.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable
DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor
(usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
3.1.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float and should be driven to VSS, it is therefore
recommended to connect the S line to VSS via a suitable pull-down resistor.
The VCC rise time must not vary faster than 1 V/µs.
3.1.3 Power-up and device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Operating conditions, in
Section 11: DC and AC parameters).
When VCC passes the POR threshold, the device is reset and is in the following state: Standby Power mode deselected (assuming that there is a pull-down resistor on the S line)
3.1.4 Power-down
At power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in the Standby Power mode (that is,
there should be no internal Write cycle in progress).
M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Memory organization
Doc ID 022572 Rev 1 11/32
4 Memory organization
The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization
Select (ORG) is left unconnected (or connected to VCC) the x16 organization is selected;
when Organization Select (ORG) is connected to Ground (VSS) the x8 organization is
selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set
either to VSS or VCC for minimum power consumption. Any voltage between VSS and VCC
applied to Organization Select (ORG) may increase the Standby current.
Instructions M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125
12/32 Doc ID 022572 Rev 1
5 Instructions
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in
Table 4 to Table 6. Each instruction consists of the following parts, as shown in Figure4:
READ, WRITE, WEN, WDS sequences: Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock
(C) being held low. A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of
Serial Clock (C). Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the op-code). The address bits of the byte or word that is to be accessed. For the M93C46, the
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 4). For the M93C56 and M93C66, the address is made up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8
organization (see Table6).
The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as
slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC
characteristics” tables, in Section 11: DC and AC parameters.
Table 4. Instruction set for the M93C46 X = Don't Care bit.
M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Instructions
Doc ID 022572 Rev 1 13/32
Table 5. Instruction set for the M93C56 and M93C66 X = Don't Care bit. Address bit A8 is not decoded by the M93C56. Address bit A7 is not decoded by the M93C56.
Table 6. Instruction set for the M93C76 and M93C86 X = Don't Care bit. Address bit A10 is not decoded by the M93C76. Address bit A9 is not decoded by the M93C76.
Instructions M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125
14/32 Doc ID 022572 Rev 1
5.1 Read Data from Memory
The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically increments the
internal address register and clocks out the next byte (or word) as long as the Chip Select
Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words)
and a continuous stream of data can be read.
5.2 Write Enable and Write Disable
The Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6 initializes itself so that erase and write instructions are disabled. After
an Write Enable (WEN) instruction has been executed, erasing and writing remains enabled
until an Write Disable (WDS) instruction is executed, or until VCC falls below the power-on
reset threshold voltage. To protect the memory contents from accidental corruption, it is
advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read
Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write
Disable (WDS) instructions.
M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125 Instructions
Doc ID 022572 Rev 1 15/32
Figure 4. READ, WRITE, WEN, WDS sequences For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table6.
5.3 Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Instructions M93C86-125 M93C76-125 M93C66-125 M93C56-125 M93C46-125
16/32 Doc ID 022572 Rev 1
5.4 Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is
automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase
instruction before a Write Data to Memory (WRITE) instruction.
Figure 5. ERASE, ERAL sequences For the meanings of An and Xn, please see Table 4, Table 5 and Table6.
5.5 Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section6:
READY/BUSY status.
