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M87C257
ADDRESS LATCHED 256K (32K X 8) UV EPROM AND OTP ROM
ADDRESS LATCHED
256K (32K x 8) UV EPROM and OTP EPROM
June 1996 1/13
Figure 1. Logic DiagramINTEGRATED ADDRESS LATCH
FAST ACCESS TIME: 45ns
LOW POWER “CMOS” CONSUMPTION: Active Current 30mA Standby Current 100μA
PROGRAMMING VOLTAGE: 12.75V
ELECTRONIC SIGNATURE for AUTOMATED
PROGRAMMING
PROGRAMMING TIMES of AROUND 3sec.
(PRESTO II ALGORITHM)
DESCRIPTIONThe M87C257 is a high speed 262,144 bit UV
erasable and electrically programmable EPROM.
The M87C257 incorporates latches for all address
inputs to minimize chip count, reduce cost, and
simplify the design of multiplexed bus systems.
The Window Ceramic Frit-Seal Dual-in-Line pack-
age has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M87C257 is offered in Plastic Leaded Chip Carrier,
package.
Table 1. Signal Names
Figure 2A. DIP Pin Connections
Warning: NC = Not Connected, DU = Dont’t Use.
Figure 2B. LCC Pin Connections
DEVICE OPERATION The modes of operation of the M87C257 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL levels
except for VPP and 12V on A9 for Electronic Signa-
ture.
Read Mode The M87C257 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
Table 2. Absolute Maximum Ratings (1)
M87C257
Note: X = VIH or VIL, VID = 12V ± 0.5V
Table 3. Operating Modes
Table 4. Electronic Signaturebe used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable (AS = VIH) or latched (AS =
VIL), the address access time (tAVQV) is equal to the
delay from E to output (tELQV). Data is available at
the output after delay of tGLQV from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least tAVQV-tGLQV.
The M87C257 reduces the hardware interface in
multiplexed address-data bus systems. The proc-
essor multiplexed bus (AD0-AD7) may be tied to
the M87C257’s address and data pins. No sepa-
rate address latch is needed because the
M87C257 latches all address inputs when AS is
low.
Standby Mode The M87C257 has a standby mode which reduces
the active current from 30mA to 100μA (Address
Stable). The M87C257 is placed in the standby
mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are
in a high impedance state, independent of the G
input.
Two Line Output Control Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines, should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is desired from a particular memory device.
M87C257
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
Table 5. AC Measurement Conditions
Note: 1. Sampled only, not 100% tested.
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
System Considerations The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can
be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1μF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7μF bulk electrolytic capacitor should be used
between VCC and VSS for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
M87C257
Notes:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Maximum DC voltage on Output is VCC +0.5V.
Table 7. Read Mode DC Characteristics (1)(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested. In case of 45ns speed see High Speed AC measurement conditions.
Table 8A. Read Mode AC Characteristics (1)(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M87C257
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Table 8B. Read Mode AC Characteristics (1)(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Figure 5. Read Mode AC Waveforms
M87C257
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 9. Programming Mode DC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
Table 10. Programming Mode AC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Programming When delivered (and after each erasure for UV
EPROM), all bits of the M87C257 are in the "1"
state. Data is introduced by selectively program-
ming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a "0" to a "1" is by die exposition to ultra-
violet light (UV EPROM). The M87C257 is in the
programming mode when VPP input is at 12.75V, G
is at VIH and E is pulsed to VIL. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25 V ± 0.25 V.
M87C257
