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M74HCT7259B1R
(OPEN DRAIN, INVERTING OUTPUT) 8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER
1/13September 2001 LOW POWER DISSIPATION:
ICC =4μA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : IH = 2V (MIN.) VIL = 0.8V (MAX) HIGH CURRENT OPEN DRAIN OUTPUT UP
TO 80 mA
DESCRIPTIONThe M74HCT7259 is an high speed CMOS 8 BIT
ADDRESSABLE LATCH/DECODER fabricated
with silicon gate C2 MOS technology.
This device has single data input (D) 8 LATCH
inverted OUTPUTS (Q0 - Q7), 3 address inputs
(A, B and C), common enable input (ENABLE)
and a common CLEAR input. To operate this
device as an addressable latch, data is held on the
D input, and the address of the latch into which the
data is to be entered is held on the A, B and C
inputs.
When ENABLE is taken low the data flows
through to the address output. The data is stored
on the positive going edge of the ENABLE pulse.
All unaddressed latches will remain unaffected.
With ENABLE in the high state the device is
deselected and all latches remain in their previous
state, unaffected by changes on the data or
address inputs. To eliminate the possibility of
entering erroneous data into the latches, the
ENABLE should be held high (inactive) while the
address lines are changing. If ENABLE is held
high and CLEAR is taken low all eight latches are
cleared to the HIGH (OFF) state. If ENABLE is low
all latches except the addressed latch will be
cleared. The address latch will instead be the
complement of the D input, effectively
implementing a 3 to 8 line decoder. Internal clamp
diodes protect the open drain outputs against over
voltages due to inductive loads.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT7259 8 BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER
OPEN DRAIN, INVERTING OUTPUT
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT72592/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE D : The level at the data input
Qi0 : The level before the indicated steady state input conditions were established, (i = 0, 1,...., 7)
M74HCT72593/13
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HCT72594/13
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HCT72595/13
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
M74HCT72596/13
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
M74HCT72597/13
WAVEFORM 2 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM PULSE WIDTH, SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
