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M74HCT646B1R
OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
1/13July 2001 HIGH SPEED:
fMAX = 60 MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS : IH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 646
DESCRIPTIONThe 74HCT646 is an advanced high-speed
CMOS OCTAL BUS TRANSCEIVER AND
REGISTER (3-STATE) fabricated with silicon gate2 MOS technology.
This device consists of bus transceiver circuits
with 3 state, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus will be clocked
into register on the low to high transition of the
appropriate clock pin (Clock AB or Clock BA).
Enable (G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the
high-impedance port may be stored in either
register or in both. The select controls (Select AB
select BA) can multiplex stored and real time
(transparent mode) data. The direction control
determines which bus will receive data when
enable G is active (low). In the isolation mode
(enable G high), "A" data may be stored in one
register and/or "B" data may be stored in the other
register. When an output function is disabled, the
input function is still enabled and may be used to
store and transmit data. Only one of the two
buses, A or B, may be driven at a time.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT646OCTAL BUS TRANSCEIVER/REGISTER
WITH 3 STATE OUTPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT6462/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
M74HCT6463/13
LOGIC DIAGRAM
TIMING CHART
M74HCT6464/13
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HCT6465/13
DC SPECIFICATIONS
M74HCT6466/13
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per bit)
M74HCT6467/13
TEST CIRCUIT CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
