M74HCT540 ,HCT540: INVERTEDM74HCT540OCTAL BUS BUFFERWITH 3 STATE OUTPUTS (INVERTED) ■ HIGH SPEED:t = 12ns (TYP.) at V = 4.5VP ..
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M74HCT540RM13TR ,OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)M74HCT540OCTAL BUS BUFFERWITH 3 STATE OUTPUTS (INVERTED) ■ HIGH SPEED:t = 12ns (TYP.) at V = 4.5VP ..
M74HCT541M1R ,OCTAL BUS BUFFER WITH WITH 3 STATE OUTPUTS (NON INVERTED)ABSOLUTE MAXIMUM RATINGS Symbol Parameter ValueUnitV Supply Voltage-0.5 to +7 VCCV DC Input Vo ..
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M74HCT540
HCT540: INVERTED
1/9August 2001 HIGH SPEED:
tPD = 12ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS : IH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 540
DESCRIPTIONThe 74HCT540 is an advanced high-speed
CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with silicon gate C2 MOS technology.
The M74HCT540 is an inverting buffer.
The 3-STATE control gate operates as a two input
AND such that if either G1 and G2 are high, all
eight output are in the high impedance state. In
order to enhance PC board layout the
M74HCT540 offer a pinout having inputs and
outputs on opposite sides of the package.
The M74HCT540 is designed to directly interface
HSC2 MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT540OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT5412/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
Z : High Impedance
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HCT5413/9
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
M74HCT5414/9
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per circuit)
TEST CIRCUIT CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
M74HCT5415/9
WAVEFORM 1: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
