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M74HCT174M1R-M74HCT174RM13TR-M74HCT174TTR
HEX D-TYPE FLIP FLOP WITH CLEAR
1/10August 2001 HIGH SPEED :
fMAX = 56MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:CC =4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS : IH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
DESCRIPTIONThe M74HCT174 is an high speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C2 MOS technology.
Information signals applied to D inputs are
transferred to the Q output on the positive going
edge of the CLOCK (CK) pulse. When the CLEAR
(CLR) input is held low, the Q outputs are held low
independently of the other inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT174HEX D-TYPE FLIP FLOP WITH CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT1742/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays
M74HCT1743/10
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HCT1744/10
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/6 (per FLIP/
FLOP)
And the total CPD when N pcs of FLIP-FLOP operate can be gained by the following equation : CPD (total) = 38 + 15 x n
M74HCT1745/10
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK), SETUP AND
HOLD TIME (nD TO CLOCK), CLOCK MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
M74HCT1746/10
WAVEFORM 2 : PROPAGATION DELAY TIME (nQ TO CLEAR)(f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM PULSE WIDTH (CLEAR), MINIMUM REMOVAL TIME (CLEAR TO
CLOCK)(f=1MHz; 50% duty cycle)
