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M74HCT138M1R-M74HCT138RM13TR
3 TO 8 LINE DECODER (INVERTING)
1/9August 2001 HIGH SPEED:
tPD = 16ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS :
VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
DESCRIPTIONThe M74HCT138 is an high speed CMOS 3 TO 8
LINE DECODER fabricated with silicon gate2 MOS technology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go high. Three
enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT1383 TO 8 LINE DECODER (INVERTING)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT1382/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HCT1383/9
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HCT1384/9
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
M74HCT1385/9
WAVEFORM 1: PROPAGATION DELAYS FOR INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
WAVEFORM 2: PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS (f=1MHz; 50% duty cycle)
