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M74HCT132B1R-M74HCT132M1R
QUAD 2-INPUT SCHMITT NAND GATE
1/8July 2001 HIGH SPEED:
tPD = 19ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:
ICC = 1μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY :
VH = 0.7V (TYP) at Vcc = 4.5V BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
DESCRIPTIONThe M74HCT132 is an high speed CMOS QUAD
2-INPUT SCHMITT NAND GATE fabricated with
silicon gate C2 MOS technology.
Pin configuration and function are the same as
those of the M74HCT00. The hysteresis
characteristics (around 20% Vcc ) of all inputs allow
slowly changing input signals to be transformed
into sharply defined jitter-free output signals.
The M74HCT132 is designed to directly interface
HSC2 MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT132QUAD 2-INPUT SCHMITT NAND GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT1322/8
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HCT1323/8
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
M74HCT1324/8
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
