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M74HCT125M1R-M74HCT125RM13TR
QUAD BUS BUFFERS (3-STATE)
1/9August 2001 HIGH SPEED:
tPD = 13ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:CC = 4μA(MAX.) at TA =25°C COMPATIBLE WITH TTL OUTPUTS : IH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
DESCRIPTIONThe M74HCT125 is an high speed CMOS QUAD
BUFFER (3-STATE) fabricated with silicon gate2 MOS technology.
The device requires the 3-STATE control input G
to be set high to place the output in to the high
impedance state.
The M74HCT125 is designed to directly interface
HSC2 MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT125QUAD BUS BUFFER (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT1252/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HCT1253/9
DC SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
M74HCT1254/9
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω))
M74HCT1255/9
WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)
