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M74HC74B1
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
4HC74M74HC74DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
B1R(Plastic Package)
ORDER CODES:M54HC74F1R M74HC74M1R
M74HC74B1R M74HC74C1R
F1R(CeramicPackage)
M1R(MicroPackage)
C1R(Chip Carrier)
PIN CONNECTIONS (top view)= Internal
INPUT AND OUTPUT EQUIVALENT CIRCUIT HIGH SPEED
fMAX=71 MHz (TYP.) AT VCC =5V. LOWPOWER DISSIPATION
ICC =2 μA (MAX.) ATTA =25°C. HIGH NOISE IMMUNITY
VNIH =VNIL =28% VCC (MIN.). OUTPUT DRIVE CAPABILITY LSTTL LOADS. SYMMETRICAL OUTPUT IMPEDANCE
IOH =IOL=4 mA (MIN.). BALANCEDPROPAGATION DELAYS
tPLH =tPHL. WIDE OPERATING VOLTAGE RANGE
VCC (OPR)=2V TO6V. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS74
The M54/74HC74isa high speed CMOS DUALD
TYPE FLOP WITH PRESET AND CLEAR fabri-
catedin silicon gateC2 MOS technology.It has the
same high speed performanceof LSTTL combined
with trueCMOSlow power consumption. Asignalon
the DINPUTis transferredto theQ OUTPUT during
the positive going transitionof the clock pulse.
CLEAR and PRESET are independentof the clock
and accomplishedby alowon the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
DESCRIPTION
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION13 1CLR,
2CLR
Asyncronous Reset-
Direct Input12 1D,2D Data Inputs11 1CK, 2CK Clock Input
(LOW-to-HIGH, Edge-
Triggered)10 1PR, 2PR Asyncronous Set- Direct
Input9 1Q,2Q True Flip-Flop Outpus8 1Q,2Q Complement Flip-Flop
Outputs GND Ground (0V) VCC Positive Supply Voltage
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS OUTPUTS FUNCTIONCLR PR D CK Q Q H X X L H CLEAR L X X H L PRESET X X H H L L H
HHH H L X Qn Qn NO CHANGE Don’tCare
LOGIC DIAGRAM
M54/M74HC74
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value UnitVCC Supply Voltage 2to6 V Input Voltage 0to VCC V Output Voltage 0to VCC V
Top Operating Temperature:
M54HC Series
M74HC Series
-55to +125
-40to +85CC
tr,tf Input Rise and Fall Time VCC=2V 0to 1000 ns
VCC=4.5V 0to 500
VCC=6V 0to 400
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage -0.5to+7 V DC Input Voltage -0.5to VCC+ 0.5 V DC Output Voltage -0.5to VCC+ 0.5 V
IIK DC Input Diode Current ±20 mA
IOK DC Output Diode Current ±20 mA DC Output Source Sink Current Per Output Pin ±25 mA
ICCor IGND DC VCCor Ground Current ±50 mA Power Dissipation 500(*) mW
Tstg Storage Temperature -65to +150 oC Lead Temperature (10 sec) 300 oC
Absolute MaximumRatings arethose values beyond whichdamage tothedevicemayoccur.Functional operation under theseconditionisnotimplied.
(*)500 mW:≅65oC derate to300mWby 10mW/oC:65o Cto85oC
M54/M74HC74
SPECIFICATIONSSymbol Parameter
Test Conditions Value
UnitVCC(V)
=25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.VIH High Level Input
Voltage
2.0 1.5 1.5 1.54.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Low Level Input
Voltage
2.0 0.5 0.5 0.54.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH High Level
Output Voltage
2.0 VI=
VIH
VIL
IO=-20μA
1.9 2.0 1.9 1.94.5 4.4 4.5 4.4 4.4
6.0 5.9 6.0 5.9 5.9
4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10
6.0 IO=-5.2 mA 5.68 5.8 5.63 5.60
VOL Low Level Output
Voltage
2.0 VI=
VIH
VIL
IO=20μA
0.0 0.1 0.1 0.14.5 0.0 0.1 0.1 0.1
6.0 0.0 0.1 0.1 0.1
4.5 IO= 4.0 mA 0.17 0.26 0.33 0.40
6.0 IO= 5.2 mA 0.18 0.26 0.33 0.40 Input Leakage
Current 6.0 VI =VCCor GND ±0.1 ±1 ±1 μA
ICC Quiescent Supply
Current
6.0 VI =VCCor GND 2 20 40 μA
M54/M74HC74
ELECTRICAL CHARACTERISTICS (CL =50 pF, Inputtr =tf =6 ns)
Symbol Parameter
Test Conditions Value
UnitVCC(V)
=25oC
54HC and 74HC
-40to85oC
74HC
-55to 125oC
54HC
Min. Typ. Max. Min. Max. Min. Max.tTLH
tTHL
Output Transition
Time
2.0 30 75 95 1104.5 8 151922
6.0 7 131619
tPLH
tPHL
Propagation
Delay Time
(CLOCK-Q)
2.0 48 150 190 2254.5 16 30 38 45
6.0 13 26 32 38
tPLH
tPHL
Propagation
Delay Time
(CL, PR-Q)
2.0 51 150 190 2254.5 17 30 38 45
6.0 15 26 32 38
fMAX Maximum Clock
Frequency
2.0 6.2 21 5 4.2
MHz4.5 31 63 25 21
6.0 37 67 30 25
tW(H)
tW(L)
Minimum Pulse
Width
(CLOCK)
2.0 18 75 95 1104.5 6 151922
6.0 6 131619
tW(L) Minimum Pulse
Width
(CL, PR)
2.0 21 75 95 1104.5 7 151922
6.0 6 131619 Minimum Set-up
Time
2.0 15 75 95 1104.5 4 151922
6.0 3 131619 Minimum Hold
Time
2.0 0 0 04.5 0 0 0
6.0 0 0 0
tREM Minimum
Removal Time
(CL, PR)
2.0 0 2530354.5 0 5 6 7
6.0 0 4 5 6
CIN Input Capacitance 5 10 10 10 pF
CPD(*) Power Dissipation
Capacitance pF
(*) CPD isdefinedasthe valueofthe IC’sinternal equivalent capacitance which iscalculated fromthe operatingcurrent consumption without load.
(Referto Test Circuit).Average operting currentcanbe obtained bythefollowingequation. ICC(opr)=CPD •VCC •fIN+ICC/2(per FLIP/FLOP)
M54/M74HC74
SWITCHING CHARACTERISTICS TEST
WAVEFORM
TEST CIRCUIT ICC (Opr.)
SWITCHING CHARACTERISTICS TEST WAVEFORM(K= VCC)
INPUTTRANSIENTTIMEISTHESAMEASTHAT CASEOF SWITCHING CHARACTERISTICS
TEST.F2=F1/2
M54/M74HC74
