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M74HC73
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
1/11August 2001 HIGH SPEED :
fMAX = 80MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC =2μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 73
DESCRIPTIONThe M74HC73 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C2 MOS technology.
Depending on the logic level applied to J and K
inputs, this device changes state on the negative
going transition of clock input pulse (CK). The
clear function is accomplished independently of
the clock condition when the clear input (CLR) is
taken low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC73DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC732/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM
M74HC733/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC734/11
DC SPECIFICATIONS
M74HC735/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/
FLOP)
M74HC736/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: MINIMUM REMOVAL TIME (f=1MHz; 50% duty cycle)
