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M74HC595B1R-M74HC595M1R-M74HC595RM13TR-M74HC595TTR
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)
1/14July 2001 HIGH SPEED:
fMAX = 59MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 6mA (MIN.) FOR QA to QH
|IOH| = IOL = 4mA (MIN.) FOR QH’
� BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 595
DESCRIPTIONThe M74HC595 is an high speed CMOS 8-BIT
SHIFT REGISTERS/OUTPUT LATCHES
(3-STATE) fabricated with silicon gate C2 MOS
technology.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. The storage register has 8 3-STATE
outputs. Separate clocks are provided for both the
shift register and the storage register.
The shift register has a direct-overriding clear,
serial input, and serial output (standard) pins for
cascading. Both the shift register and storage
register use positive-edge triggered clocks. If both
clocks are connected together, the shift register
state will always be one clock pulse ahead of the
storage register.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC5958 BIT SHIFT REGISTER
WITH OUTPUT LATCHES (3 STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC5952/14
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X: Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HC5953/14
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
TIMING CHART
M74HC5954/14
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC5955/14
DC SPECIFICATIONS
