M74HC573 ,HC563 INVERTINGM74HC573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUT NON INVERTING ■ HIGH SPEED:t = 13ns (TYP.) at V = 6V ..
M74HC573M1R ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT (NON INVERTING)M74HC573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUT NON INVERTING ■ HIGH SPEED:t = 13ns (TYP.) at V = 6V ..
M74HC573RM13TR ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT (NON INVERTING)ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage-0.5 to +7 VCCV DC Input V ..
M74HC573RM13TR ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT (NON INVERTING)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
M74HC574M1R ,OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT (NON INVERTING)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
M74HC574M1R ,OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUT (NON INVERTING)ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage-0.5 to +7 VCCV DC Input V ..
MAX1487EESA+T ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplicationsPART TEMP RANGE PIN-PACKAGELow-Power RS-485 TransceiversMAX481ECPA 0°C to +70°C 8 Plast ..
MAX1487EPA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversGeneral Description ________
MAX1487EPA+ ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 Transceiversapplications that are not ESD sensitive see the pin-and function-compatible MAX481, MAX483, MAX485, ..
MAX1487ESA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversApplications ______________Ordering InformationLow-Power RS-485 TransceiversPART TEMP. RANGE PIN-PA ..
MAX1487ESA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsMAX481C/D 0°C to +70°C Dice*Industrial-Control Local Area NetworksOrdering Information ..
MAX1487ESA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversApplications ______________Ordering InformationLow-Power RS-485 TransceiversPART TEMP. RANGE PIN-PA ..
M74HC573
HC563 INVERTING
1/12July 2001 HIGH SPEED:
tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
DESCRIPTIONThe M74HC573 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C2 MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely. When
LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while is at high level the outputs will be
in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC573OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC5732/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X: Don’t Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
M74HC5733/12
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC5734/12
DC SPECIFICATIONS
M74HC5735/12
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
M74HC5736/12
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip
Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 33 + 18 x n (pF)
TEST CIRCUIT CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
