M74HC533 ,HC373 NON INVERTINGM74HC533OCTAL D-TYPE LATCHWITH 3 STATE OUTPUT INVERTING ■ HIGH SPEED: t = 12ns (TYP.) at V = 6VPD ..
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M74HC533M1R ,OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT (NON INVERTING)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
M74HC540M1R ,OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
M74HC540M1R ,OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (INVERTED)M74HC540OCTAL BUS BUFFERWITH 3 STATE OUTPUTS (INVERTED) ■ HIGH SPEED:t = 9ns (TYP.) at V = 6VPD CC ..
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MAX1487E ,±15kV ESD-Protected, Slew-Rate Limited, Low-Power, RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX1487ECPA ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 TransceiversGeneral Description ________
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MAX1487ECSA+T ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplications:ceivers on the bus. The MAX488E–MAX491E areMAX3483E/MAX3485E/MAX3486E/MAX3488E/designe ..
M74HC533
HC373 NON INVERTING
1/11August 2001 HIGH SPEED:
tPD = 12ns (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 533
DESCRIPTIONThe M74HC533 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C2 MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input. When the LE is
taken, the Q outputs will be latched at the logic
level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while high level the outputs will be in a
high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC533OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC5332/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X: Don’t Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
M74HC5333/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC5334/11
DC SPECIFICATIONS
M74HC5335/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip
Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 22 + 16 x n (pF)
M74HC5336/11
TEST CIRCUIT CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
