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M74HC51M1R-M74HC51RM13TR
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE
1/9August 2001 HIGH SPEED:
tPD = 11ns (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC = 1μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 51
DESCRIPTIONThe M74HC51 is an high speed CMOS DUAL 2
WIDE 2 INPUT AND/OR INVERT GATE
fabricated with silicon gate C2 MOS technology.
It contains a 2-WIDE 2-INPUT AND/OR INVERT
GATE and a 2-WIDE 3-INPUT AND/OR
INVERT GATE.
The internal circuit is composed of 3 stages (2
INPUT) or 5 stages (3 INPUT) including buffer
output, which enables high noise immunity and
stable output.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC51DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC512/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
TRUTH TABLE X : Don’t Care
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
M74HC513/9
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HC514/9
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
M74HC515/9
WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
