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M74HC4543M1R-M74HC4543RM13TR
BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER
1/10July 2001 HIGH SPEED:
tPD = 14ns (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4543
DESCRIPTIONThe M74HC4543 is an high speed CMOS
BCD-TO-7 SEGMENT DECODER WITH LCD
DRIVER fabricated with silicon gate C2 MOS
technology.
This device consists of BCD-TO-7 segment
decoder with a BCD input latch and a 7-segment
driver for a liquid crystal display (LCD). When any
illegal BCD input signal is applied or input BI is
held high, the display is blanked. When driving
LCDs, a common square wave signal should be
applied not only to the PH input of this device but
also to the electrically common backplane of the
display. For other types of readouts, such as
light-emitting diode (LED), some additional
drivers, such as a transistor array is required. All
inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC4543 BCD TO 7 SEGMENT LATCH/DECODER/LCD DRIVER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC45432/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
↑ : Same as above combinations
### : Depends upon the BCD code previously applied when LD =’H’
M74HC45433/10
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
DISPLAY MODE
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
M74HC45434/10
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HC45435/10
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per
FLIP/FLOP)
M74HC45436/10
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM : PROPAGATION DELAY, SETUP AND HOLD TIMES, MINIMUM PULSE WIDTH (LD) (f=1MHz; 50% duty cycle)