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M74HC4094M1R-M74HC4094RM13TR
8 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
1/12January 2003 HIGH SPEED:
fMAX =80MHz (TYP.)at VCC =6V LOW POWER DISSIPATION:CC =4μA(MAX.)atTA =25°C HIGH NOISE IMMUNITY:NIH =VNIL =28%VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH|=IOL =4mA (MIN) BALANCED PROPAGATION DELAYS: PLH≅t PHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR)= 2Vto 6V PIN AND FUNCTION COMPATIBLE WITH SERIES 4094
DESCRIPTIONThe M74HC4094is an high speed CMOS8 BIT
SIPO SHIFT LATCH REGISTER fabricated with
silicon gateC2 MOS technology.
This device consistsof an8bit shift register and8 bit latch with3 state output buffer. Datais
shifted serially trough the shift register on the
positive going transitionof the clock input signal.
Theoutputof thelast stage (Qs) canbeusedto
cascade several devices.
Data on the Qs outputis transferredtoa second
output (Qs’)on the following negative transitionof
the clock input signal. The dataof each stageof
the shift registeris provided witha latch, which
latches dataon the negative going transitionof the
STROBE input signal. When the STROBE inputis
held high, data propagates through the latchtoa
3-state output buffer.
This bufferis enabled when OUTPUT ENABLE
inputis taken high.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC4094 BIT SIPO SHIFT LATCH REGISTER (3-STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC40942/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE: Don’t Care: High Impedance
NC:No Change
LOGIC DIAGRAMThis logic diagramhasnotbe usedto estimate propagation delays
M74HC40943/12
TIMING CHART
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied
(*) 500mWat65°C; derateto 300mWby 10mW/°Cfrom 65°Cto85°C
M74HC40944/12
RECOMMENDED OPERATING CONDITIONS SPECIFICATIONS
M74HC40945/12
ELECTRICAL CHARACTERISTICS(CL=50 pF, Inputtr=tf =6ns)
M74HC40946/12
CAPACITIVE CHARACTERISTICS CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load. (Referto Test Circuit). Average operating currentcanbe obtainedbythe following equation.ICC(opr)=CPD xVCC xfIN+ICC/2(per FLIP/
FLOP)
TEST CIRCUIT= 50pF/150pFor equivalent (includesjigand probe capacitance) =1KΩor equivalent =ZOUTof pulse generator (typically 50Ω)
