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M74HC4040
HC4040 12 STAGE BINARY COUNTER, HC4020 14 STAGE BINARY COUNTER
1/11July 2001 HIGH SPEED :
fMAX = 70 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC =4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4040
DESCRIPTIONThe M74HC4040 is an high speed CMOS 12
STAGE BINARY COUNTER fabricated with
silicon gate C2 MOS technology.
A clear input is used to reset the counter to the all
low level state. A high level on CLEAR
accomplishes the reset function. A negative
transition on the CLOCK input increments the
counter by one.
For M74HC4040 each division stage has an
output; the final frequency is 1/4096 fIN. All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC404012 STAGE BINARY COUNTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC40402/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HC40403/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC40404/11
DC SPECIFICATIONS
M74HC40405/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/
FLOP)
M74HC40406/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: MINIMUM PULSE WIDTH (CLEAR) AND REMOVAL TIME (CLEAR TO CLOCK) (f=1MHz; 50% duty cycle)
