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M74HC194M1R
4 BIT PIPO SHIFT REGISTER
1/12August 2001 HIGH SPEED :
tPD = 13 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC =4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 194
DESCRIPTIONThe M74HC194 is an high speed CMOS 8 BIT
PIPO SHIFT REGISTER fabricated with silicon
gate C2 MOS technology. This SHIFT REGISTER
is designed to incorporate virtually all of the
features a system designer may want in a shift
register. It features parallel inputs, parallel
outputs, right shift and left shift serial inputs, clear
line. The register has four distinct modes of
operation : PARALLEL (Broadside) LOAD ; SHIFT
RIGHT(SR) (in the direction QA QD); SHIFT
LEFT(SL); INHIBIT CLOCK (do nothing).
Synchronous parallel loading is accomplished by
applying the four data bits and taking both mode
control inputs, S0 and S1 high. The data are
loaded into their respective flip-flops and appear
at the outputs after the positive transition of the
CLOCK input. During loading, serial data flow is
inhibited. Shift right is accomplished
synchronously with the rising edge of the clock
pulse when S0 is high and S1 is low. Serial data
for this mode is entered at the SHIFT RIGHT data
input. When S0 is low and S1 is high, data shift left
synchronously and new data is entered at the
SHIFT LEFT serial input. Clocking of the flip-flops
is inhibited when both mode control inputs are low.
The mode control inputs should be changed only
when the CLOCK input is high.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC1944 BIT PIPO SHIFT REGISTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC1942/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
a ~ d : The level of steady state input voltage at input A ~ D
QA0 ~ QD0 : No Change
QAn ~ QDn : The level of QA, QB, QC, respectively, before the most recent positive transition of the clock.
M74HC1943/12
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
TIMING CHART
M74HC1944/12
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC1945/12
DC SPECIFICATIONS
M74HC1946/12
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
