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M74HC112B1R-M74HC112M1R-M74HC112RM13TR
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
1/12July 2001 HIGH SPEED :
fMAX = 79MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:CC =2μA(MAX.) at TA =25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 112
DESCRIPTIONThe M74HC112 is an high speed CMOS DUAL
J-K FLIP-FLOP WITH PRESET AND CLEAR
fabricated with silicon gate C2 MOS technology.
The M74HC112 dual JK flip-flop features
individual J, K, clock, and asynchronous set and
clear inputs for each flip-flop. When the clock goes
high, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs
may be allowed to change when the clock pulse is
high and the bistable will function as shown in the
truth table. Input data is transferred to the input on
the negative going edge of the clock pulse.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC112DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC1122/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HC1123/12
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC1124/12
DC SPECIFICATIONS
M74HC1125/12
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/
FLOP)
M74HC1126/12
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD
TIME (J to CK) (f=1MHz; 50% duty cycle)
