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M74HC107B1R-M74HC107M1R-M74HC107RM13TR
DUAL J-K FLIP FLOP WITH CLEAR
1/11August 2001 HIGH SPEED :
fMAX = 80MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC =2μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 107
DESCRIPTIONThe M74HC107 is an high speed CMOS DUAL
J-K FLIP FLOP fabricated with silicon gate2 MOS technology. These flip-flop are edge
sensitive to the clock input and change state on
the negative going transition of the clock pulse.
Each one has independent J, K, CLOCK, and
CLEAR input and Q and Q outputs. CLEAR is
independent of the clock and accomplished by a
logic low on the input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC107DUAL J-K FLIP FLOP WITH CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC1072/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
LOGIC DIAGRAM
M74HC1073/11
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC1074/11
DC SPECIFICATIONS
M74HC1075/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/
FLOP)
M74HC1076/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: MINIMUM REMOVAL TIME (f=1MHz; 50% duty cycle)
