M74DW66500B70ZT ,2x 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 32Mbit Pseudo SRAM, 3V Supply, Multiple Memory ProductAbsolute Maximum Ratings 11DC AND AC PARAMETERS . 12Table 4. Operating and AC Measurement ..
M74HC00M1R ,QUAD 2-INPUT NAND GATEM74HC00QUAD 2-INPUT NAND GATE ■ HIGH SPEED:t = 8ns (TYP.) at V = 6VPD CC■ LOW POWER DISSIPATION:I ..
M74HC00M1R ,QUAD 2-INPUT NAND GATEABSOLUTE MAXIMUM RATINGS Symbol Parameter Value UnitV Supply Voltage-0.5 to +7 VCCV DC Input V ..
M74HC00RM13TR ,QUAD 2-INPUT NAND GATEM74HC00QUAD 2-INPUT NAND GATE ■ HIGH SPEED:t = 8ns (TYP.) at V = 6VPD CC■ LOW POWER DISSIPATION:I ..
M74HC00TTR ,QUAD 2-INPUT NAND GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
M74HC02B1R ,QUAD 2-INPUT NOR GATEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
MAX1270BENG ,Multirange / +5V / 8-Channel / Serial 12-Bit ADCs
MAX1270BENG+ ,Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
MAX1271ACNG+ ,Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
MAX1271ACNG+ ,Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
MAX1271AEAI ,Multirange / +5V / 8-Channel / Serial 12-Bit ADCs
MAX1271AEAI+ ,Multirange, +5V, 8-Channel, Serial 12-Bit ADCs
M74DW66500B70Z-M74DW66500B70ZT
2x 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 32Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
1/19
PRELIMINARY DATASeptember 2003
M74DW66500B2x 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and
32Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
FEATURES SUMMARY MULTIPLE MEMORY PRODUCT Two 64Mbit (8M x8 or 4M x16), Multiple Bank,
Page, Boot Block, Flash Memories 32Mbit (2M x 16) Pseudo Static RAM SUPPLY VOLTAGE
–VCCF = VCCP = 2.7 to 3.3V
–VPPF = 12V for Fast Program (optional) ACCESS TIME: 70, 90ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 227Eh + 2202h + 2201h
EACH FLASH MEMORY ASYNCHRONOUS PAGE READ MODE Page Width: 4 Words Page Access: 25, 30ns Random Access: 70, 90ns PROGRAMMING TIME 10µs per Byte/Word typical 4 Words/ 8 Bytes at-a-time Program MEMORY BLOCKS Quadruple Bank Memory Array:
8Mbits+ 24Mbits + 24Mbits + 8Mbits Parameter Blocks (at both Top and Bottom) DUAL OPERATIONS While Program or Erase in a group of banks
(from 1 to 3), Read in any of the other banks PROGRAM/ERASE SUSPEND and RESUME
MODES Read from any Block during Program
Suspend Read and Program another Block during
Erase Suspend UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming
Figure 1. Package VPP/WP PIN for FAST PROGRAM and WRITE
PROTECT TEMPORARY BLOCK UNPROTECTION
MODE COMMON FLASH INTERFACE 64 bit Security Code EXTENDED MEMORY BLOCK Extra block used as security block or to store
additional information 100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM ACCESS TIME: 70ns BYTE CONTROL: UB/LB PROGRAMMABLE PARTIAL ARRAY 8 WORD PAGE ACCESS CAPABILITY: 18ns
(max) LOW STANDBY CURRENT: 100µA
M74DW66500B2/19
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash-1 Chip Enable (EF1) and Flash-2 Chip Enable (EF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Reset/Block Temporary Unprotect (RPF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PSRAM Chip Enable inputs (E1P, E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VCCF Supply Voltage (2.7 to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VCCP Supply Voltage (2.7 to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
FLASH MEMORY DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 6. Flash DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 7. PSRAM DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
M74DW66500B
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline15
Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . .16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 10. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
M74DW66500B4/19
SUMMARY DESCRIPTION
Table 1. Signal Names
M74DW66500B
M74DW66500B6/19
SIGNAL DESCRIPTIONSee Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). Address lines A0-A20
are common inputs for the Flash Memory and
PSRAM components. Address line A21 is an input
that is common for the two Flash Memory compo-
nents. The Address Inputs select the cells in the
memory array to access during Bus Read opera-
tions. During Bus Write operations they control the
commands sent to the Command Interface of the
internal state machine. The Flash memory is ac-
cessed through the Chip Enable (EF) and Write
Enable (W) signals, while the PSRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (W).
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–
1). When BYTE is High, VIH, this pin behaves as
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Flash-1 Chip Enable (EF1) and Flash-2 Chip En-
able (EF2). The Chip Enable input activates the
memory to which it is attached, allowing Bus Read
and Bus Write operations to be performed. When
Chip Enable is High, VIH, all other pins are ig-
nored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the Flash Memory
and PSRAM components.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the Flash Memory and
PSRAM components.
VPP/Write Protect (VPP/WP). The VPP/Write
Protect pin provides two functions. The VPP func-
tion allows the Flash memory to use an external
high voltage power supply to reduce the time re-
quired for Program operations. This is achieved
by bypassing the unlock cycles and/or using the
multiple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware meth-
od of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the ad-
dress space).
When VPP/Write Protect is Low, VIL, the memory
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while VPP/Write Protect is Low, even when RPF is
at VID.
When VPP/Write Protect is High, VIH, the memory
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
When VPP/Write Protect is raised to VPP the mem-
ory automatically enters the Unlock Bypass mode.
When VPP/Write Protect returns to VIH or VIL nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
VIH to VPP and from VPP to VIH must be slower
than tVHVPP. See the M29DW640D datasheet for
more details.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should be connected be-
tween the VPP/Write Protect pin and the VSS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, IPP.
Reset/Block Temporary Unprotect (RPF). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if VPP/WP is at VIL, then the two outer-
most boot blocks will remain protected even if RPF
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
M74DW66500BtRHEL, whichever occurs last. See the
M29DW640D datasheet for more details.
Holding RPF at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the Flash memory is performing a Program
or Erase operation. During Program or Erase op-
erations Ready/Busy is Low, VOL. Ready/Busy is
high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
Flash memory. When Byte/Word Organization Se-
lect is Low, VIL, the Flash memory is in x8 mode,
when it is High, VIH, the Flash memory is in x16
mode.
PSRAM Chip Enable inputs (E1P, E2P). The
Chip Enable inputs activate the PSRAM control
logic, input buffers and decoders. E1P at VIH with
E2P at VIH deselects the memory, reducing the
power consumption to the standby level, whereas
E2P at VIL deselects the memory and reduces the
power consumption to the Power-down level, re-
gardless of the level of E1P. E1P and E2P can also
be used to control writing to the PSRAM memory
array, while WP remains at VIL. It is not allowed to
set EF1 or EF2 at VIL, E1P at VIL and E2P at VIH at
the same time.
PSRAM Upper Byte Enable (UBP). The Upper
Byte Enable input enables the upper byte for
PSRAM (DQ8-DQ15). UBP is active low.
PSRAM Lower Byte Enable (LBP). The Lower
Byte Enable input enables the lower byte for
PSRAM (DQ0-DQ7). LBP is active low.
VCCF Supply Voltage (2.7 to 3.3V). VCCF pro-
vides the power supply for Flash memory opera-
tions (Read, Program and Erase).
The Command Interface is disabled when the
VCCF Supply Voltage is less than the Lockout Volt-
age, VLKO. This prevents Bus Write operations
from accidentally damaging the data during power
up, power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCCF Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, ICC3.
VCCP Supply Voltage (2.7 to 3.3V). VCCP pro-
vides the power supply for the PSRAM.
VSS Ground. VSS is the ground reference for all
voltage measurements in the Flash and PSRAM
chips.
M74DW66500B8/19
FUNCTIONAL DESCRIPTIONThe Flash Memory and PSRAM components have
a common power supply. The components are dis-
tinguished by four chip enable inputs: EF1 for one
Flash memory, EF2 for the other, and E1S and E2S
for the PSRAM.
Recommended operating conditions do not allow
more than one of the Flash Memory or PSRAM
component to be in active mode at the same time.
The most common example is simultaneous read
operations on the Flash Memory and PSRAM
components which would result in a data bus con-
tention. Therefore it is recommended to put two of
the components in the high impedance state when
reading from the third (see Table 2 Main Operation
Modes for details).
Table 2. Main Operation ModesNote:1. X = Don’t Care (VIL or VIH). UBP and LBP are tied together. This table is valid when BYTE = VIH. This table is also valid when BYTE = VIL, with the only difference that DQ15-DQ8 are always
high impedance when the Flash Memory components are being accessed. For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in
the stacked product. To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the
“Auto Select Command” in the M29DW640D datasheet.
M74DW66500B
Figure 4. Functional Block Diagram
M74DW66500B10/19
FLASH MEMORY DEVICESThe M74DW66500B contains two 64Mbit Flash
memories. For detailed information on how to use
these, see the M29DW640D datasheet, which is
available on the STMicroelectronics web site,
.
PSRAM DEVICEThe M74DW66500B contains a 32Mbit Pseudo
SRAM. For detailed information on how to use it,
see the M69AW048B datasheet, which is avail-
able from your local STMicroelectronics distribu-
tor.
