M69AW024BL60ZB8T ,16 MBIT (1M X16) 3V SUPPLY, ASYNCHRONOUS PSRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 4. Operating and ..
M6M80011L , 1024 BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM
M6M80021 , 2048 BIT ELECTRICALLY ERASABLE AND RPOGRAMMABLE ROM
M6M80021FP , 2048 BIT ELECTRICALLY ERASABLE AND RPOGRAMMABLE ROM
M6M80021FP , 2048 BIT ELECTRICALLY ERASABLE AND RPOGRAMMABLE ROM
M6MF16S2AVP , CMOS 3.3V-ONLY FLASH MEMORY & CMOS STATIC RAM STACKED-MCP
MAX1132BEAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceELECTRICAL CHARACTERISTICS(AV = DV = +5V ±5%, f = 4.8MHz, external clock (50% duty cycle), 24 clock ..
MAX1133BCAP ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceELECTRICAL CHARACTERISTICS(AV = DV = +5V ±5%, f = 4.8MHz, external clock (50% duty cycle), 24 clock ..
MAX1133BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceFeaturesThe MAX1132/MAX1133 are 200ksps, 16-bit ADCs.♦ 200ksps (Bipolar) and 150ksps (Unipolar) The ..
MAX1133BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications. The MAX1132 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX1133BEAP ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceFeaturesThe MAX1132/MAX1133 are 200ksps, 16-bit ADCs. 200ksps (Bipolar) and 150ksps (Unipolar) The ..
MAX1133BEAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications such as indus-trial process control, instrumentation, and medical♦ 2.5µA Shutdown Mode
M69AW024BL60ZB8T
16 MBIT (1M X16) 3V SUPPLY, ASYNCHRONOUS PSRAM
1/29September 2004
M69AW024B16 Mbit (1M x16) 3V Asynchronous PSRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns, 70ns LOW STANDBY CURRENT: 70µA DEEP POWER DOWN CURRENT: 10µA LOW VCC DATA RETENTION: 2.3V COMPATIBLE WITH STANDARD LPSRAM
M69AW024B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Deep Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 5. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. Read and Standby Modes AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7. Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 8. Chip Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 9. Address Access After G Control, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . .16
3/29
M69AW024BFigure 10.Address Access After E1 Control, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . .16
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.E1 Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 12.W Controlled, Single Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 13.W Controlled, Continuous Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 14.E1 Controlled, Read/Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 15.E1 Controlled, Read/Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 16.G Controlled Read, W Controlled Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 17.G Controlled Read, W Controlled Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . . .22
Table 9. Power Down and Power-Up AC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 18.Standby Mode Entry AC Waveforms, After Read or Write . . . . . . . . . . . . . . . . . . . . . . .23
Figure 19.Power-down AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 20.Power-up Mode AC Waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 21.Power-up Mode AC Waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 22.Power-up Mode AC Waveforms - 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 10. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 23.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 24.TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Outline, Bottom View . . . .26
Table 11. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Mechanical Data. . . . . . . .26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
M69AW024B
SUMMARY DESCRIPTIONThe M69AW024B is a 16 Mbit (16,777,216 bit)
CMOS memory, organized as 1,048,576 words by
16 bits, and is supplied by a single 2.7V to 3.3V
supply voltage range.
M69AW024B is a member of STMicroelectronics
PSRAM memory family, based on the one-transis-
tor per-cell architecture. These devices are manu-
factured using dynamic random access memory
cells, to minimize the cell size, and maximize the
amount of memory that can be implemented in a
given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AW024B han-
dles the periodic refresh cycle, automatically, and
without user involvement.
Write cycles can be performed on a single byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip Enable (E1) or in deep power down mode by
using Chip Enable (E2).
Power-Down mode achieves a very low current
consumption by halting all the internal activities.
Since the refresh circuitry is halted, the duration of
the power-down should be less than the maximum
period for refresh, if the user has not finished with
the data contents of the memory.
Table 1. Signal Names
5/29
M69AW024B
M69AW024B
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Read and Write operations.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low.
Data Inputs/Outputs (DQ0-DQ7). The Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E1). When asserted (Low), the
Chip Enable, E1, activates the memory state ma-
chine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
Chip Enable (E2). The Chip Enable, E2, puts the
device in Deep Power-down mode when it driven Low. This is the lowest power mode.
Output Enable (G). The Output Enable, G, pro-
vides a high speed tri-state control, allowing fast
read/write cycles to be achieved with the common
I/O data bus.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory.
Upper Byte Enable (UB). The Upper Byte En-
able, UB, gates the data on the Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte En-
able, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read or
Write) and for driving the refresh logic, even when
the device is not being accessed.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
7/29
M69AW024B
M69AW024B
Table 2. Operating Modes
Note:1. X = VIH or VIL. Output Disable mode should not be kept longer than 1µs. Power-down mode can be entered from Stand-by state, and all DQ pins are in Hi-Z state. Can be either VIL or VIH but must be valid before Read or Write. Byte Read is not supported. Either or both LB and UB must be Low, VIL, for Read operations.
9/29
M69AW024B
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see Table 2.).
Power On Sequence
Because the internal control logic of the
M69AW024B needs to be initialized, the following
power-on procedure must be followed before the
memory is used: Apply power and wait for VCC to stabilize Wait 400µs while driving both Chip Enable
signals (E1 and E2) High Activate the memory by driving Chip
Enable (E1) Low.
Read Mode
The device is in Read mode when: Write Enable (W) is High and Output Enable (G) Low and the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The time taken to enter Read mode (tELQV, tGLQV
or tBLQV) depends on which of the above signals
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate
during tELQX, tGLQX and tBLQX, but data will always
be valid during tAVQV.
Write Mode
The device is in Write mode when Write Enable (W) is Low and Chip Enable (E1) is Low and the two Chip Enable signals are asserted
(E1 is Low, and E2 is High) one of Upper Byte Enable (UB) or Lower
Byte Enable (LB) is Low, while the other is
High.
The Write cycle begins just after the event (the fall-
ing edge) that causes the last of these conditions
to become true (tAVWL or tAVEL or tAVBL).
The Write cycle is terminated by the earlier of a ris-
ing edge on Write Enable (W) or Chip Enable (E1).
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB) or Lower Byte Enable (LB) is Low), then
Write Enable (W) will return the outputs to high im-
pedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for tDVWH before
the rising edge of Write Enable (W), or for tDVEH
before the rising edge of Chip Enable (E1), which-
ever occurs first, and remain valid for tWHDX, tEHDX
Standby Mode
The device is in Standby mode when: Chip Enable (E1)is High and Chip Enable (E2)is High.
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array con-
tinues to be refreshed. In this mode, the memory
current consumption, ISB, is reduced, and the data
remains valid.
Deep Power-down Mode
The device is in Deep Power-down mode when: Chip Enable (E2 is Low).
M69AW024B
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied.
Table 3. Absolute Maximum Ratings
11/29
M69AW024B
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Note:1. All voltages are referenced to VSS. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 9.
M69AW024B
Table 5. Capacitance
Note:1. Outputs deselected.
Table 6. DC Characteristics
Note:1. Average AC current, Outputs open, cycling at tAVAX (min). Maximum DC voltage on input and I/O pins is VCC +0.3V.
During voltage transitions, input may positive overshoot to VCC+ 1.0V for a period of up to 5ns. Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may positive overshoot to VSS+ 1.0V for a period of up to 5ns.
13/29
M69AW024B
Table 7. Read and Standby Modes AC Characteristics
M69AW024B
Note:1. CL = 50pF with 1 TTL and R1=50Ω. CL = 5pF tELQV is applicable if G is brought to Low before E1 goes Low and if actual value of either tAVGL1 or tELGL, or both, is shorter than
the specified value. Only applicable to A0, A1 and A2 when both and G and E1 are kept Low for Address access. Applicable if G is brought to Low before E1 goes Low. tAVGL1, tELGL(Min) and tGHGL1(Min) are reference values when the access time is determined by tGLQV. If the actual value of each
parameter is lower than the specified minimum values, tGLQV is increased by the difference between the actual value and the spec-
ified minimum value. tAVGL2 and tGHGL2 correspond to absolute minimum values during G controlled access. tAXAV is applicable when two or more addresses from A0 to A2 are switched from the previous state. If the actual value of tELGL or tGHGL1 is lower than the specified minimum value, tGLAX and tGLEH will be equal to tAVAX(Min)−
tELGL (Actual) and tAVAX (Min) − tGHGL1 (Actual), respectively.
10. The maximum value is applicable if E1 is kept Low.
15/29
M69AW024B
