M69AR024BL-70ZB8 ,16 Mbit (1M x16) 1.8V Supply, Asynchronous PSRAMBlock Diagram . . 7OPERATION . . . . . . 8Power Up Sequence . . . . 8Read Mod ..
M69AR048BL70ZB8 ,32 MBIT (2M X16) 1.8V SUPPLY, ASYNCHRONOUS PSRAMfeatures several Power-Down modes,random access memory cells, to minimize the cellmaking of power s ..
M69AW024BE60ZB8F , 16 Mbit (1M x16) 3V Asynchronous PSRAM
M69AW024BE60ZB8F , 16 Mbit (1M x16) 3V Asynchronous PSRAM
M69AW024BL60ZB8T ,16 MBIT (1M X16) 3V SUPPLY, ASYNCHRONOUS PSRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 4. Operating and ..
M6M80011L , 1024 BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM
MAX1132BCAP ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications. The MAX1132 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceMAX1132/MAX113319-2083; Rev 0; 8/0116-Bit ADC, 200ksps, 5V Single-Supplywith Reference
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications. The MAX1132 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX1132BEAP ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BEAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
M69AR024BL70ZB8-M69AR024BL-70ZB8
16 Mbit (1M x16) 1.8V Supply, Asynchronous PSRAM
M69AR024B16 Mbit (1M x16) 1.8V Supply, Asynchronous PSRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 1.7 to 2.25V ACCESS TIME: 70ns, 80ns LOW STANDBY CURRENT: 110µA DEEP POWER DOWN CURRENT: 10µA COMPATIBLE WITH STANDARD LPSRAM TRI-STATE COMMON I/O
Figure 1. Package
M69AR024B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Upper Byte Enable (UB).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Deep Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 8. Address and Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . .14
Figure 9. LB/UB Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
M69AR024BTable 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 10.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 12.Write Enable and UB/LB Controlled, Write AC Waveforms 1 . . . . . . . . . . . . . . . . . . . . .18
Figure 13.Write Enable and UB/LB Controlled, Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . .19
Figure 14.Write Enable and UB/LB Controlled, Write AC Waveforms 3 . . . . . . . . . . . . . . . . . . . . .19
Figure 15.Write Enable and UB/LB Controlled, Write AC Waveforms 4 . . . . . . . . . . . . . . . . . . . . .20
Figure 16.Chip Enable Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . . . . . .21
Figure 17.E, W, G Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . .21
Figure 18.Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms . . .22
Figure 19.G, W and UB/LB Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . .22
Table 9. Standby Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 20.Power Down Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 21.Power-Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 22.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 23.TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm Pitch, Package Outline, Bottom
View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 10. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm Pitch, Package Mechanical Data . .25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
M69AR024B
SUMMARY DESCRIPTIONThe M69AR024B is a 16 Mbit (16,777,216 bit)
CMOS memory, organized as 1,048,576 words by
16 bits, and is supplied by a single 1.7V to 2.25V
supply voltage range.
M69AR024B is a member of STMicroelectronics
1T/1C (one transistor per cell) memory family.
These devices are manufactured using dynamic
random access memory cells, to minimize the cell
size, and maximize the amount of memory that
can be implemented in a given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AR024B han-
dles the periodic refresh cycle, automatically, and
without user involvement.
Write cycles can be performed on a single byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip Enable (E1) or in deep power down mode by
using Chip Enable (E2).
Power-Down mode achieves a very low current
consumption by halting all the internal activities.
Since the refresh circuitry is halted, the duration of
the power-down should be less than the maximum
period for refresh, if the user has not finished with
the data contents of the memory.
Table 1. Signal Names
M69AR024B
M69AR024B
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Read and Write operations.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low.
Data Inputs/Outputs (DQ0-DQ7). The Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E1). When asserted (Low), the
Chip Enable, E1, activates the memory state ma-
chine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
Chip Enable (E2). The Chip Enable, E2, puts the
device in Deep Power-down mode when it driven Low. This is the lowest power mode.
Output Enable (G). The Output Enable, G, pro-
vides a high speed tri-state control, allowing fast
read/write cycles to be achieved with the common
I/O data bus.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the device.
Upper Byte Enable (UB). The Upper Byte En-
able, UB, gates the data on the Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte En-
able, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read or
Write) and for driving the refresh logic, even when
the device is not being accessed.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
M69AR024B
Figure 4. Block Diagram
M69AR024B
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see Table
2., Operating Modes).
Power Up Sequence
Because the internal control logic of the
M69AR024B needs to be initialized, the following
power-on procedure must be followed before the
memory is used: Apply power and wait for VCC to stabilize Wait 300µs while driving both Chip Enable
signals (E1 and E2) High
Read Mode
The device is in Read mode when: Write Enable (W) is High and Output Enable (G) Low and Upper Byte Enable (UB) or Lower Byte
Enable (LB) is Low, or both the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The time taken to enter Read mode (tELQV, tGLQV
or tBLQV) depends on which of the above signals
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate
during tELQX, tGLQX and tBLQX, but data will always
be valid during tAVQV.
Write Mode
The device is in Write mode when Write Enable (W) is Low and Upper Byte Enable (UB) or Lower Byte
Enable (LB) is Low, or both the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The Write cycle begins just after the event (the fall-
ing edge) that causes the last of these conditions
to become true (tAVWL or tAVEL or tAVBL).
The Write cycle is terminated by the earlier of a ris-
ing edge on Write Enable (W) or Chip Enable (E1).
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB) or Lower Byte Enable (LB) is Low), then
Write Enable (W) will return the outputs to high im-
pedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for tDVWH before
the rising edge of Write Enable (W), for tDVEH be-
fore the rising edge of Chip Enable (E1), or for tD-
VBH before the rising edge of Byte Enable (LB,UB),
whichever occurs first, and remain valid for tWHDZ,
tEHDZ or tBHDZ.
Standby Mode
The device is in Standby mode when: Chip Enable (E1)is High and Chip Enable (E2)is High
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array con-
tinues to be refreshed. In this mode, the memory
current consumption, ISB, is reduced, and the data
remains valid.
Deep Power-down Mode
The device is in Deep Power-down mode when: Chip Enable (E2)is Low
M69AR024B
Table 2. Operating Modes
Note:1. X = VIH or VIL. Should not be kept in this logic condition longer than 1µs. Please contact your local ST sales office for the relaxation of 1 µs limitation. Power-down mode can be entered from the Standby state, and all DQ pins are in High-Z state. Can be either VIL or VIH but must be valid before Read or Write.
M69AR024B
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings" table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability.
Table 3. Absolute Maximum Ratings
Note:1. The minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, inputs may undershoot VSS by 1.0V for periods
of up to 5ns. The maximum DC voltage on input and I/O pins is VCC+0.2V. During voltage transitions, inputs may overshoot VCC by 1.0V for
periods of up to 5ns.
M69AR024B
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Note:1. All voltages are referenced to VSS.
Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit
M69AR024B
Table 5. Capacitance
Note:1. Sampled only, not 100% tested. Outputs deselected.
Table 6. DC Characteristics
Note:1. The maximum DC voltage on input and I/O pins is VCC+0.2V. During voltage transitions, inputs may overshoot VCC by 1.0V for
periods of up to 5ns. The minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, inputs may undershoot VSS by 1.0V for periods
of up to 5ns.
M69AR024B
Table 7. Read Mode AC Characteristics
Note:1. Maximum value is applicable if E1 is kept at Low without change of address input of A3 to A19. If needed by system operation,
please contact local ST sales office for the relaxation of 1µs limitation. Address should not be changed within tAVAX(min). The output load 50pF with 50Ω termination to VCC*0.5 V. The output load CL = 5pF without any other load. Applicable to A3 to A19 when E1 is kept at Low. Applicable only to A0, A1 and A2 when E1 is kept at Low for the page address access. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs. Applicable when at least two of address inputs among applicable are switched from previous state. tAVAX(min) must be satisfied.
M69AR024B
Figure 7. Address Controlled, Read Mode AC Waveforms
Note: E2 = High, W = High.
Figure 8. Address and Output Enable Controlled, Read Mode AC Waveforms
Note: W = High, E2 = High.
