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M68Z128-55N1
5V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable
1/12March 2000
M68Z1285V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable ULTRA LOW DATA RETENTION CURRENT
–10nA (typical) 2.0μA (max) OPERATION VOLTAGE: 5V ±10% 128Kb x 8 VERY FAST SRAM with OUTPUT
ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER AUTOMATIC POWER-DOWN WHEN
DESELECTED INTENDED FOR USE WITH ST
ZEROPOWER® AND TIMEKEEPER®
CONTROLLERS
DESCRIPTIONThe M68Z128 is a 1 Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
5V ±10% supply, and all inputs and outputs are
TTL compatible.
Table 1. Signal Names
M68Z128
Table 2. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Up to a maximum operating VCC of 5.5V only. One output at a time, not to exceed 1 second duration.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68Z128 is available in TSOP32 (8 x 20mm)
package.
READ MODEThe M68Z128 is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and both Chip Enables (E1 and E2) are as-
serted. This provides access to data from eight of
the 1,048,576 locations in the static memory array,
specified by the 17 address inputs. Valid data will
be available at the eight output pins within tAVQV
after the last stable address, providing G is Low,
E1 is Low and E2 is High. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (tE1LQV,
tE2HQV, or tGLQV) rather than the address. Data out
may be indeterminate at tE1LQX, tE2HQX and tGLQX,
but data lines will always be valid at tAVQV.
WRITE MODEThe M68Z128 is in the Write mode whenever the
W and E1 pins are Low, with E2 High. Either the
Chip Enable inputs (E1 and E2) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of both Chip
Enables being active with W low. Therefore, ad-
dress setup time is referenced to Write Enable and
both Chip Enables as tAVWL, tAVE1L and tAVE2H re-
spectively, and is determined by the latter occur-
ring edge.
The Write cycle can be terminated by the earlier
rising edge of E1, W, or the falling edge of E2.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for tDVWH before
the rising edge of Write Enable, or for tDVE1H be-
fore the rising edge of E1 or for tDVE2L before the
3/12
M68Z128falling edge of E2, whichever occurs first, and re-
main valid for tWHDX, tE1HDX or tE2LDX.
OPERATIONAL MODEThe M68Z128 has a Chip Enable power down fea-
ture which invokes an automatic standby mode
whenever either Chip Enable is de-asserted (E1 =
High or E2 = Low). An Output Enable (G) signal
provides a high speed tri-state control, allowing
fast read/write cycles to be achieved with the com-
mon I/O data bus. Operational modes are deter-
mined by device control inputs W, E1, and E2 as
summarized in the Operating Modes table.
Table 3. Operating Modes Note:1. X = VIH or VIL.
Table 4. AC Measurement ConditionsNote: Output Hi-Z is defined as the point where data is no longer
driven.
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Note:1. Sampled only, not 100% tested. Outputs deselected.
M68Z128
Table 6. DC Characteristics (TA = 0 to 70°C; VCC = 5V ±10%)
Note:1. Average AC current, Outputs open, cycling at tAVAV minimum. All other Inputs at VIL ≤ 0.8V or VIH ≥ 2.2V. All other Inputs at VIL ≤ 0.3V or VIH ≥ VCC –0.3V.
5/12
M68Z128
Table 7. Read and Standby Modes AC Characteristics
(TA = 0 to 70°C; VCC = 5V ±10%)Note:1. CL = 100pF. CL = 5pF. At any given temperature and voltage condition, tEIHQZ + tEZHQZ is less than tEILQX and tEZLQX, tGHQZ is less than tGLQX for any
given device.
M68Z128
