M68AW512-ML70ND6 ,8 MBIT (512K X16) 3.0V ASYNCHRONOUS SRAMLogic Diagram Table 1. Signal NamesA0-A16 Address InputsVCCDQ0-DQ15 Data Input/OutputE Chip Enable1 ..
M68Z128 ,5V, 1 Mbit (128Kb x8) Low Power SRAM with Output EnableAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....4DC AND AC ..
M68Z128-55N1 ,5V / 1 Mbit 128Kb x8 Low Power SRAM with Output EnableAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M69AR024BL70ZB8 ,16 Mbit (1M x16) 1.8V Supply, Asynchronous PSRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. TFBGA Connections (Top view t ..
M69AR024BL70ZB8 ,16 Mbit (1M x16) 1.8V Supply, Asynchronous PSRAMAbsolute Maximum Ratings . . . . . . . 10DC and AC PARAMETERS . 11Table 4. Operating and ..
M69AR024BL-70ZB8 ,16 Mbit (1M x16) 1.8V Supply, Asynchronous PSRAMBlock Diagram . . 7OPERATION . . . . . . 8Power Up Sequence . . . . 8Read Mod ..
MAX1106EUB+T ,Single-Supply, Low-Power, Serial 8-Bit ADCsApplicationsMAX1107CUB 0°C to +70°C 10 μMAXPortable Data LoggingMAX1107EUB -40°C to +85°C 10 μMAXHa ..
MAX1108CUB ,Single-Supply / Low-Power / 2-Channel / Serial 8-Bit ADCsMAX1108/MAX110919-1399; Rev 0; 10/98Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
MAX1108EUB+T ,Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCsApplicationsMAX1108EUB -40°C to +85°C 10 µMAXPortable Data LoggingMAX1109CUB 0°C to +70°C 10 µMAXHa ..
MAX1109CUB ,Single-Supply / Low-Power / 2-Channel / Serial 8-Bit ADCsELECTRICAL CHARACTERISTICS—MAX1108(V = +2.7V to +3.6V; unipolar input mode; COM = GND, f = 500kHz, ..
MAX1109CUB ,Single-Supply / Low-Power / 2-Channel / Serial 8-Bit ADCsApplicationsMAX1108EUB -40°C to +85°C 10 µMAXPortable Data LoggingMAX1109CUB 0°C to +70°C 10 µMAXHa ..
MAX1109CUB ,Single-Supply / Low-Power / 2-Channel / Serial 8-Bit ADCsApplicationsMAX1108EUB -40°C to +85°C 10 µMAXPortable Data LoggingMAX1109CUB 0°C to +70°C 10 µMAXHa ..
M68AW512ML70ND6-M68AW512-ML70ND6
8 MBIT (512K X16) 3.0V ASYNCHRONOUS SRAM
1/19September 2004
M68AW512M8 Mbit (512K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.6V 512K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN
M68AW512M
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . .10
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . .10
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 11.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 12.UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 13.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 14.TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . .16
Table 10. TSOP 44 TypeII - 44 lead Plastic Thin Small Outline TypeII, Package Mechanical Data16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3/19
M68AW512M
SUMMARY DESCRIPTIONThe M68AW512M is a 8 Mbit (8,388,608 bit)
CMOS SRAM, organized as 524,288 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW512M is available in TSOP44 Type II
packages.
Table 1. Signal Names
M68AW512M
5/19
M68AW512M
M68AW512M
OPERATION
The M68AW512M has a Chip Enable power down
feature which invokes an automatic standby mode
whenever either Chip Enable is de-asserted= High) or LB and UB are de-asserted (LB and
UB = High). An Output Enable (G) signal provides
a high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus. Operational modes are by
device control inputs W, E, LB and UB as summa-
rized in the Operating Modes table (see Table 2).
Read Mode
The M68AW512M is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight or sixteen,
pending on the status of the signal UB and LB, of
the 8,388,608 locations in the static memory array,
specified by the 19 address inputs. Valid data will
be available at the eight or sixteen output pins
within tAVQV after the last stable address, provid-
ing G is Low and E is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (tELQV,
tGLQV or tBLQV) rather than the address. Data out
may be indeterminate at tELQX, tGLQX and tBLQX
but data lines will always be valid at tAVQV.
Write Mode
The M68AW512M is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted during Address transitions for
subsequent write cycles. When E (W) is Low, and
UB or LB is Low, write cycle begins on the W (E)'s
falling edge. When E and W are Low, and UB = LB
= High, write cycle begins on the first falling edge
of UB or LB. Therefore, address setup time is
referenced to Write Enable, Chip Enable or UB/LB
as tAVWL, tAVEL and tAVBL respectively, and is
determined by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB.
If the Output is enabled (E = Low, G = Low, LB or= Low), then W will return the outputs to high
impedance within tWLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for tDVWH
before the rising edge of Write Enable, or for tDVEH
before the rising edge of E, or for tDVBH before the
rising edge of UB/LB whichever occurs first, and
remain valid for tWHDX, tEHDX and tBHDX respec-
tively.
Table 2. Operating Modes
Note:1. X = VIH or VIL.
7/19
M68AW512M
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1 sec periods may
affect device reliability. Refer also to the STMicro-
electronics SURE Program and other relevant
quality documents.
Table 3. Absolute Maximum Ratings
Note:1. One output at a time, not to exceed 1 second duration. Up to a maximum operating VCC of 3.6V only.
M68AW512M
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
9/19
M68AW512M
Table 5. Capacitance
Note:1. Sampled only, not 100% tested. At TA = 25°C, f = 1 MHz, VCC = 3.0V.
Table 6. DC Characteristics
Note:1. Average AC current, cycling at tAVAV minimum. E = VIL, LB OR/AND UB = VIL, VIN = VIL OR VIH. E ≤ 0.2V, LB OR/AND UB ≤ 0.2V, VIN ≤ 0.2V OR VIN ≥ VCC –0.2V. Output disabled.
M68AW512M
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
Note: Write Enable (W) = High.
