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M68AW256ML70ND6-M68AW256-ML70ND6-M68AW256ML70ND6T
4 MBIT (256K X16) 3.0V ASYNCHRONOUS SRAM
1/23April 2004
M68AW256M4 Mbit (256K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.6V 256K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns,
70ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN TSOP44, and TFBGA48 PACKAGES Compliant with Lead-Free Soldering Pro-
cesses Standard or Lead-Free Option
M68AW256M
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Output Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . .12
Figure 10.Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . .12
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 13.UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 14.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 15.TSOP44 II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . .18
Table 10. TSOP 44 II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . .18
Figure 16.TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Bottom View Package Outline19
Table 11. TFBGA48 6x8mm - 6x8 active ball array, 0.75 mm pitch, Package Mechanical Data . .19
Figure 17.TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . .20
3/23
M68AW256MTable 12. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . .20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
M68AW256M
SUMMARY DESCRIPTIONThe M68AW256M is a 4 Mbit (4,194,304 bit)
CMOS SRAM, organized as 262,144 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW256 is available in TFBGA48 (6x8mm
- 6x8 active ball array, 0.75mm pitch), TFBGA48
(7x8mm - 6x8 active ball array, 0.75 mm pitch) and
in TSOP44 Type II packages.
In addition to the standard version, both packages
are also available in Lead-free version, in compli-
ance with the JEDEC Std J-STD-020B, the ST
ECOPACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
Table 1. Signal Names
5/23
M68AW256M
M68AW256M
7/23
M68AW256M
M68AW256M
OPERATION
The device has four standard operating modes:
Output Disabled, Read, Write and Standby/Pow-
er-Down. These modes are determined by the
control inputs E, W, G, LB and UB as summarized
in Table 2., Operating Modes.
Output Disabled. The Output Enable signal, G,
provides high-speed tri-state control of DQ0-
DQ15, allowing fast read/write cycles on the I/O
data bus. The device is in Output Disabled mode
when Output Enable, G, is High. In this mode, LB
and UB are Don’t care and DQ0-DQ15 are high
impedance.
Read Mode. The M68AW256M is in the Read
mode whenever Write Enable (W) is High with
Output Enable (G) Low, and Chip Enable (E) is as-
serted.
This provides access to data from eight or sixteen,
depending on the status of the signal UB and LB,
of the 4,194,304 locations in the static memory ar-
ray, specified by the 18 address inputs.If only one
of the Byte Enable inputs is at VIL, the
M68AW256M is in Byte Read mode. If the two
Byte Enable inputs are at VIL, the M68AW256M is
in Word Read mode. So depending on the status
of the UB and LB signals, valid data will be avail-
able on the lower eight, the upper eight or all six-
teen output pins, tAVQV after the last stable
address, providing G is Low and E is Low.
If either of E or G is asserted after tAVQV has
elapsed, data access will be measured from the
limiting parameter (tELQV, tGLQV or tBLQV) rather
than the address. Data out may be indeterminate
at tELQX, tGLQX and tBLQX but data lines will always
be valid at tAVQV.
Write Mode. The M68AW256M is in the Write
mode whenever the W and E are Low. Either the
Chip Enable input (E) or the Write Enable input
(W) must be de-asserted during Address
transitions for subsequent write cycles. When E
(W) is Low, and UB or LB is Low, write cycle
begins on the W (E)'s falling edge. When E and W
are Low, and UB = LB = High, write cycle begins
on the first falling edge of UB or LB. Therefore,
address setup time is referenced to Write Enable,
Chip Enable or UB/LB as tAVWL, tAVEL and tAVBL
respectively, and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB. If the Output is en-
abled (E = Low, G = Low, LB or UB= Low), then
W will return the outputs to high impedance within
tWLQZ of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for tDVWH before the rising
edge of Write Enable, or for tDVEH before the rising
edge of E, or for tDVBH before the rising edge of
UB/LB whichever occurs first, and remain valid for
tWHDX, tEHDX and tBHDX respectively.
Standby/Power-Down. The M68AW256M has a
Chip Enable power down feature which invokes an
automatic standby mode whenever either Chip
Enable is de-asserted (E= High) or LB and UB are
de-asserted (LB and UB = High). An Output En-
able (G) signal provides a high speed tri-state con-
trol, allowing fast read/write cycles to be achieved
with the common I/O data bus. Operational modes
are determined by device control inputs W, E, LB
and UB as summarized in the Operating Modes ta-
ble (see Table 2).
Table 2. Operating Modes
Note:1. X = VIH or VIL.
9/23
M68AW256M
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Note:1. One output at a time, not to exceed 1 second duration. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assermbly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. Not exceeding 250°C for more than 30s, and peaking at 260°C. Up to a maximum operating VCC of 3.6V only.
M68AW256M
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
11/23
M68AW256M
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
M68AW256M
Note: Write Enable (W) = High.
