M68AW128ML55ND1 ,2 Mbit (128K x16) 3.0V Asynchronous SRAMAbsolute Maximum Ratings 9DC AND AC PARAMETERS . 10Table 4. Operating and AC Measurement ..
M68AW128ML55ND6 ,2 Mbit (128K x16) 3.0V Asynchronous SRAMFEATURES SUMMARY■ SUPPLY VOLTAGE: 2.7 to 3.6V Figure 1. Packages■ 128K x 16 bits SRAM with OUTPUT E ..
M68AW128ML55ZB6 ,2 MBIT (128K X16) 3.0V ASYNCHRONOUS SRAMfeatures fully static operation re- In addition to the standard version, the packagesquiring no ext ..
M68AW128ML70ND1 ,2 Mbit (128K x16) 3.0V Asynchronous SRAMfeatures fully static operation re- In addition to the standard version, the packagesquiring no ext ..
M68AW128ML70ND6 ,2 MBIT (128K X16) 3.0V ASYNCHRONOUS SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. TSOP Connections . . . ..
M68AW128-ML70ND6 ,2 MBIT (128K X16) 3.0V ASYNCHRONOUS SRAMBlock Diagram . . 7OPERATION . . . . . . 8Read Mode . . . . 8Write Mode ..
MAX11014BGTM , Automatic RF MESFET Amplifier Drain-Current Controllers
MAX11014BGTM+ ,Automatic RF MESFET Amplifier Drain-Current ControllersApplicationsto +5.25V digital supply (1.5mA typical supply current),and a -4.5V to -5.5V negative s ..
MAX1101CWG ,Single-Chip / 8-Bit CCD Digitizer with Clamp and 6-Bit PGAELECTRICAL CHARACTERISTICS(V = V = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µ ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsential analog input range is ±2.2V when using the internal • 117dB SNR at 1ksps referen ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCElectrical Characteristics(V = +3.0V to +3.6V, V = +2.7V to V , f = 24.576MHz, f = 16ksps, V = +2.5 ..
MAX11040KGUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsDRDYOUTAIN1+24-BIT DIGITALADC FILTERAIN1-● Power-Protection Relay Equipment REGISTERS A ..
M68AW128ML55ND1-M68AW128ML55ND6-M68AW128ML70ND1
2 Mbit (128K x16) 3.0V Asynchronous SRAM
M68AW128M2 Mbit (128K x16) 3.0V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.6V 128K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN PACKAGES Compliant with Lead-Free Soldering
Processes Lead-Free Versions
Figure 1. Packages
M68AW128M
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . .12
Figure 10.Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . .13
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 13.UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 14.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Figure 15.TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . .18
Table 10. TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 16.TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm pitch, Bottom View Package
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 11. TFBGA48 6x8mm - 6x8 Active Ball Array, 0.75mm pitch, Package Mechanical Data . .19
M68AW128M
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
M68AW128M
SUMMARY DESCRIPTIONThe M68AW128M is a 2 Mbit (2,097,152 bit)
CMOS SRAM, organized as 131,072 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW128M is available in TFBGA48
(0.75 mm pitch) and in TSOP44 Type II packages.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
Table 1. Signal Names
M68AW128M
M68AW128M
M68AW128M
M68AW128M
OPERATION
The M68AW128M has a Chip Enable power down
feature which invokes an automatic standby mode
whenever either Chip Enable is de-asserted= High) or LB and UB are de-asserted (LB and
UB = High). An Output Enable (G) signal provides
a high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus. Operational modes are determined by
device control inputs W, E, LB and UB as summa-
rized in the Operating Modes table (see Table 2).
Read Mode
The M68AW128M is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight or sixteen, de-
pending on the status of the signal UB and LB, of
the 2,097,152 locations in the static memory array,
specified by the 17 address inputs. Valid data will
be available at the eight or sixteen output pins
within tAVQV after the last stable address, provid-
ing G is Low and E is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (tELQV,
tGLQV or tBLQV) rather than the address. Data out
may be indeterminate at tELQX, tGLQX and tBLQX
but data lines will always be valid at tAVQV.
Write Mode
The M68AW128M is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted during Address transitions for
subsequent write cycles. When E (W) is Low, and
UB or LB is Low, write cycle begins on the W (E)'s
falling edge. When E and W are Low, and UB = LB
= High, write cycle begins on the first falling edge
of UB or LB. Therefore, address setup time is
referenced to Write Enable, Chip Enable or UB/LB
as tAVWL, tAVEL and tAVBL respectively, and is
determined by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB.
If the Output is enabled (E = Low, G = Low, LB or= Low), then W will return the outputs to high
impedance within tWLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for tDVWH
before the rising edge of Write Enable, or for tDVEH
before the rising edge of E, or for tDVBH before the
Table 2. Operating Modes
Note:1. X = VIH or VIL.
M68AW128M
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1s periods may
affect device reliability. Refer also to the STMicro-
electronics SURE Program and other relevant
quality documents.
Table 3. Absolute Maximum Ratings
Note:1. One output at time not to exceed 1 second duration. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. Up to a maximum operating VCC of 3.6V only.
M68AW128M
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit
M68AW128M
Table 5. Capacitance
Note:1. Sampled only, not 100% tested. At TA = 25°C, f = 1 MHz, VCC = 3.0V.
Table 6. DC Characteristics
Note:1. Average AC current, cycling at tAVAV minimum. E = VIL, LB OR/AND UB = VIL, VIN = VIL OR VIH. E ≤ 0.2V, LB OR/AND UB ≤ 0.2V, VIN ≤ 0.2V OR VIN ≥ VCC –0.2V. Output disabled.
