M68AW127BM70NK6T ,1Mbit 128K x8, 3.0V Asynchronous SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SO Connections . 5Figur ..
M68AW128ML55ND1 ,2 Mbit (128K x16) 3.0V Asynchronous SRAMAbsolute Maximum Ratings 9DC AND AC PARAMETERS . 10Table 4. Operating and AC Measurement ..
M68AW128ML55ND6 ,2 Mbit (128K x16) 3.0V Asynchronous SRAMFEATURES SUMMARY■ SUPPLY VOLTAGE: 2.7 to 3.6V Figure 1. Packages■ 128K x 16 bits SRAM with OUTPUT E ..
M68AW128ML55ZB6 ,2 MBIT (128K X16) 3.0V ASYNCHRONOUS SRAMfeatures fully static operation re- In addition to the standard version, the packagesquiring no ext ..
M68AW128ML70ND1 ,2 Mbit (128K x16) 3.0V Asynchronous SRAMfeatures fully static operation re- In addition to the standard version, the packagesquiring no ext ..
M68AW128ML70ND6 ,2 MBIT (128K X16) 3.0V ASYNCHRONOUS SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. TSOP Connections . . . ..
MAX1099CEAE ,10-Bit Serial-Output Temperature Sensors with 5-Channel ADCApplicationsMAX1098AEAE* -40°C to +85°C 16 SSOP ±0.75Temperature/Voltage Supervision ofMAX1098BEAE ..
MAX11014BGTM , Automatic RF MESFET Amplifier Drain-Current Controllers
MAX11014BGTM+ ,Automatic RF MESFET Amplifier Drain-Current ControllersApplicationsto +5.25V digital supply (1.5mA typical supply current),and a -4.5V to -5.5V negative s ..
MAX1101CWG ,Single-Chip / 8-Bit CCD Digitizer with Clamp and 6-Bit PGAELECTRICAL CHARACTERISTICS(V = V = +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µ ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCApplicationsential analog input range is ±2.2V when using the internal • 117dB SNR at 1ksps referen ..
MAX11040GUU+ ,24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCElectrical Characteristics(V = +3.0V to +3.6V, V = +2.7V to V , f = 24.576MHz, f = 16ksps, V = +2.5 ..
M68AW127BM70MC6T-M68AW127BM70MC6U-M68AW127BM70N6-M68AW127BM70NK6-M68AW127BM70NK6T
1 MBIT (128K X8), 3.0V ASYNCHRONOUS SRAM
M68AW127B1Mbit (128K x8), 3.0V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.6V 128K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
Figure 1. Packages
M68AW127B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . .11
Figure 10.Chip Enable Controlled, Standby Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 13.E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 14.E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . .16
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 15.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . .17
Figure 16.TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline . . . . . . . . . . . . . . .18
Table 11. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data . . . . . . . .18
Figure 17.TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline . . . . . . . . . . . . . .19
Table 12. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data . . . . . .19
M68AW127B
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
M68AW127B
SUMMARY DESCRIPTIONThe M68AW127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
2.7 to 3.6V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AW127B is available in SO32, TSOP32
8x20mm and TSOP32 8x13.4mm packages.
Figure 2. Logic Diagram Table 1. Signal Names
M68AW127B
M68AW127B
M68AW127B
OPERATIONThe M68AW127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 2).
Read ModeThe M68AW127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within tAVQV after the last stable address, provid-
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(tELQV or tGLQV) rather than the address. Data out
may be indeterminate at tELQX and tGLQX, but data
lines will always be valid at tAVQV.
Write ModeThe M68AW127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1 being ac-
tive with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
tAVWL and tAVEH, respectively, and is determined
by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for tDVWH before
the rising edge of Write Enable, or for tDVEH before
the rising edge of E1, whichever occurs first, and
remain valid for tWHDX or tEHDX.
Table 2. Operating ModesX = VIH or VIL.
M68AW127B
MAXIMUM RATINGStressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 3. Absolute Maximum RatingsNote:1. One output at a time, not to exceed 1 second duration. Up to a maximum operating VCC of 3.6V only.
M68AW127B
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Figure 6. AC Measurement I/O Waveform Figure 7. AC Measurement Load Circuit
M68AW127B
Table 5. CapacitanceNote:1. Sampled only, not 100% tested. At TA = 25°C, f = 1MHz, VCC = 3.0V.
Table 6. DC Characteristics Note:1. Average AC current, cycling at tAVAV minimum. E1 = VIL, E2 = VIH, VIN = VIH or VIL. E1 ≤ 0.2V or E2 ≥ VCC –0.2V, VIN ≤ 0.2V or VIN ≥ VCC –0.2V. Output disabled.
M68AW127B
Figure 8. Address Controlled, Read Mode AC WaveformsNote: E1 = Low, E2 = High, G = Low, W = High.
Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.Note: Write Enable (W) = High.
