M68AW031AM70MS6T ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMAbsolute Maximum Ratings 8DC AND AC PARAMETERS . . 9Table 4. Operating and AC Measuremen ..
M68AW031AM70MS6T ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMM68AW031A256 Kbit (32K x8) 3.0V Asynchronous SRAM
M68AW031AM70MS6U ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SO Connections . 5Figur ..
M68AW031AM70N6 ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMBlock Diagram . . 6OPERATION . . . . . . 7Read Mode . . . . 7Write Mode ..
M68AW031AM-70N6 ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1SUMMARY DESCRIPTION ..
M68AW031AM70N6T ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMfeatures fully static operation re-The M68AW031A is available in SO28 (28-leadquiring no external c ..
MAX1090ACEI ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceMAX1090/MAX109219-1640; Rev 0; 1/00400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and ..
MAX1090BCEI+ ,400ksps, +5V, 8-/4-Channel, 10-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1090/MAX1092 low-power, 10-bit analog-to-♦ 10-Bit Resolution, ±0.5 LSB Linearitydigi ..
MAX1090BEEI ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1090/MAX1092 low-power, 10-bit analog-to- 10-Bit Resolution, ±0.5LSB Linearitydigit ..
MAX1091ACEI ,250ksps / +3V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel Interfaceapplications or for other circuits with demand-ing power consumption and space requirements.TOP VIE ..
MAX1091BCEI ,250ksps / +3V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1091/MAX1093 low-power, 10-bit analog-to- 10-Bit Resolution, ±0.5LSB Linearitydigit ..
MAX1092ACEG ,400ksps / +5V / 8-/4-Channel / 10-Bit ADCs with +2.5V Reference and Parallel InterfaceApplications D6 3 22 REFD5 4 21 REFADJIndustrial Control Systems Data LoggingD4 5 20 GNDEnergy Mana ..
M68AW031AM70MS6T-M68AW031AM70MS6U-M68AW031AM70N6-M68AW031AM-70N6-M68AW031AM70N6T-M68AW031AM70NS6
256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAM
1/21October 2004
M68AW031A256 Kbit (32K x8) 3.0V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.6V 32K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55ns,
70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN
M68AW031A
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. TSOP Connections (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. TSOP Connections (Normal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . .11
Figure 11.Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 12.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 14.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Figure 15.SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Outline . . . . . . . .16
Table 10. SO28 - 28 lead Plastic Small Outline, 330 mils body width, Package Mechanical Data.16
Figure 16.TSOP28 - 28 Lead Normal Pinout Plastic Small Outline, Package Outline . . . . . . . . . .17
Table 11. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data . . .17
Figure 17.TSOP28 - 28 Lead Reverse Pinout Plastic Small Outline, Package Outline . . . . . . . . .18
Table 12. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data. . .18
3/21
M68AW031A
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
M68AW031A
SUMMARY DESCRIPTIONThe M68AW031A is a 256 Kbit (262,144 bit)
CMOS SRAM, organized as 32,768 bytes by 8
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply. This device has an au-
tomatic power-down feature, reducing the power
consumption by over 99% when deselected.
The M68AW031A is available in SO28 (28-lead
Small Outline) and TSOP28 (28-lead Thin Small
Outline, Standard and Reverse Pinout) packages.
Table 1. Signal Names
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M68AW031A
M68AW031A
7/21
M68AW031A
OPERATION
The M68AW031A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E= High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W and E as summarized in the Operat-
ing Modes table (see Table 2.).
Read Mode
The M68AW031A is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data of the 262,144 locations in
the static memory array, specified by the 15 ad-
dress inputs. Valid data will be available at the
eight output pins within tAVQV after the last stable
address, providing G is Low and E is Low. If Chip
Enable or Output Enable access times are not
met, data access will be measured from the limit-
ing parameter (tELQV or tGLQV) rather than the ad-
dress. Data out may be indeterminate at tELQX and
tGLQX but data lines will always be valid at tAVQV.
See Figures 9, 10, 11 and Table 7. for details on
Read mode AC timings and Characteristics.
Write Mode
The M68AW031A is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted during Address transitions for
subsequent write cycles. When E (W) is Low, write
cycle begins on the W (E)'s falling edge.
Therefore, address setup time is referenced to
Write Enable or Chip Enable as tAVWL and tAVEL
respectively, and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E or W.
If the Output is enabled (E = Low, G = Low), then
W will return the outputs to high impedance within
tWLQZ of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for tDVWH before the rising
edge of Write Enable, or for tDVEH before the rising
edge of E, whichever occurs first, and remain valid
for tWHDX and tEHDX respectively.
See Figures 12, 10 and Table 8. for details on
Write mode AC timings and Characteristics.
Table 2. Operating Modes
Note: X = VIH or VIL.
M68AW031A
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1s periods may
affect device reliability. Refer also to the STMicro-
electronics SURE Program and other relevant
quality documents.
Table 3. Absolute Maximum Ratings
Note:1. One output at time not to exceed 1 second duration. Compliant with the ECOPACK® 7191395 specification for Lead-free soldering processes. Not exceeding 250°C for more than 30s, and peaking at 260°C. Up to a maximum operating VCC of 3.6V only.
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M68AW031A
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
M68AW031A
Table 5. Capacitance
Note:1. Sampled only, not 100% tested. At TA = 25°C, f = 1 MHz, VCC = 3.0V.
Table 6. DC Characteristics
Note:1. Average AC current, cycling at tAVAV minimum. E = VIL, VIN = VIL or VIH. E ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ VCC –0.2V. Output disabled.
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M68AW031A
Note: E = Low, G = Low, W = High.
Note: Write Enable (W) = High.
