M68AF511AM70MC1 ,4 Mbit (512K x8), 5V Asynchronous SRAMAbsolute Maximum Ratings . 5DC AND AC PARAMETERS . . 6Table 3. Operating and AC Measurem ..
M68AF511AM70MC6U ,4 MBIT (512K X8) 5.0V ASYNCHRONOUS SRAMAbsolute Maximum Ratings 8DC AND AC PARAMETERS . . 9Table 4. Operating and AC Measuremen ..
M68AF511AM70NC6 ,4 MBIT (512K X8) 5.0V ASYNCHRONOUS SRAMFEATURES SUMMARY■ SUPPLY VOLTAGE: 4.5 to 5.5V Figure 1. Packages■ 512K x 8 bits SRAM with OUTPUT EN ..
M68AW031AM70MS6T ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMAbsolute Maximum Ratings 8DC AND AC PARAMETERS . . 9Table 4. Operating and AC Measuremen ..
M68AW031AM70MS6T ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMM68AW031A256 Kbit (32K x8) 3.0V Asynchronous SRAM
M68AW031AM70MS6U ,256 KBIT (32K X8) 3.0V ASYNCHRONOUS SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SO Connections . 5Figur ..
MAX1062ACUB+ ,14-Bit, +5V, 200ksps ADC with 10µA ShutdownELECTRICAL CHARACTERISTICS(AV = DV = +4.75V to +5.25V, f = 4.8MHz (50% duty cycle), 24 clocks/conve ..
MAX1062BCUB+ ,14-Bit, +5V, 200ksps ADC with 10µA Shutdownfeatures a separate digital supply, allowingdirect interfacing with 2.7V to 5.25V digital logic.♦ I ..
MAX1062CCUB ,14-Bit / %V / 200ksps ADC with 10A ShutdownApplicationsMotor ControlTEMP. PIN- INLPARTRANGE PACKAGE (LSB)Industrial Process ControlMAX1062ACUB ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceApplications Ordering InformationTemperature Cable/Harness Tester PIN-PART TEMP RANGE INLSensor/Mon ..
MAX1065AEUI+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceFeaturesThe MAX1065/MAX1066 14-bit, low-power successive♦ 14-Bit-Wide (MAX1065) and Byte-Wide (MAX1 ..
MAX1066AEUP+ ,Low-Power, 14-Bit Analog-to-Digital Converters with Parallel InterfaceELECTRICAL CHARACTERISTICS(AV = DV = 5V, external reference = 4.096V, C = 1µF, C = 0.1µF, T = T to ..
M68AF511AM70MC1
4 Mbit (512K x8), 5V Asynchronous SRAM
1/18October 2002
M68AF511A4 Mbit (512K x8), 5V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 4.5 to 5.5V 512K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
Figure 1. Packages
M68AF511A
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3. TSOP and SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . .9
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 11. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . . . .14
TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . . . . .14
SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . .15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3/18
M68AF511A
SUMMARY DESCRIPTIONThe M68AF511A is a 4 Mbit (4,194,304 bit) CMOS
SRAM, organized as 524,288 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
4.5 to 5.5V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AF511A is available in a 32 lead TSOP
Type II and 32 lead SO packages.
Figure 2. Logic Diagram Table 1. Signal Names
M68AF511A
Figure 3. TSOP and SO Connections
5/18
M68AF511A
Figure 4. Block Diagram
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for periods greater than 1 sec may affect
device reliability. Refer also to the STMicroelec-
tronics SURE Program and other relevant quality
documents.
Table 2. Absolute Maximum RatingsNote:1. One output at a time, not to exceed 1 second duration. Up to a maximum operating VCC of 6.0V only.
M68AF511A
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit
7/18
M68AF511A
Table 4. CapacitanceNote:1. Sampled only, not 100% tested. At TA = 25°C, f = 1MHz, VCC = 5.0V.
Table 5. DC Characteristics Note:1. Average AC current, cycling at tAVAV minimum. E = VIL, VIN = VIH or VIL.E ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ VCC – 0.2V. Output disable.
M68AF511A
OPERATIONThe M68AF511A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E = High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W and E as summarized in the Operat-
ing Modes table (Table 6).
Table 6. Operating ModesNote: X = VIH or VIL.
Read ModeThe M68AF511A is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight of the 4,194,304
locations in the static memory array, specified by
the 19 address inputs. Valid data will be available
at the eight output pins within tAVQV after the last
stable address, providing G is Low and E is Low.
If Chip Enable or Output Enable access times are
not met, data access will be measured from the
limiting parameter (tELQV or tGLQV) rather than the
address. Data out may be indeterminate at tELQX
and tGLQX, but data lines will always be valid at
tAVQV.
Figure 7. Address Controlled, Read Mode AC WaveformsNote: E = Low, G = Low, W = High.
9/18
M68AF511A
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.Note: Write Enable (W) = High.
Figure 9. Chip Enable Controlled, Standby Mode AC Waveforms
