M68AF127BM55MC6U ,1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAMBlock Diagram . . 6OPERATION . . . . . . 7Read Mode . . . . 7Write Mode ..
M68AF127BM55MC6U ,1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAMFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1
M68AF127BM55MC6U ,1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAMFEATURES SUMMARY■ SUPPLY VOLTAGE: 4.5 to 5.5V Figure 1. Packages■ 128K x 8 bits SRAM with OUTPUT EN ..
M68AF127BM70B6U ,1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAMAbsolute Maximum Ratings 8DC AND AC PARAMETERS . . 9Table 4. Operating and AC Measuremen ..
M68AF127BM70B6U ,1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAMTABLE OF CONTENTS . . . . . 2SUMMARY DESCRIPTION . . . 4Figure 2.
M68AF127BM70MC1U ,1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAMfeatures fully static operation requiring no when deselected.external clocks or timing strobes, wit ..
MAX1044CSA+ ,Switched-Capacitor Voltage ConvertersMAX1044/ICL766019-4667; Rev 1; 7/94Switched-Capacitor Voltage Converters_______________
MAX1044CSA+T ,Switched-Capacitor Voltage ConvertersFeaturesThe MAX1044 and ICL7660 are monolithic, CMOS' Miniature µMAX Packageswitched-capacitor volt ..
MAX1044EPA ,Switched-Capacitor Voltage ConvertersFeaturesThe MAX1044 and ICL7660 are monolithic, CMOS' Miniature µMAX Packageswitched-capacitor volt ..
MAX1044ESA ,Switched-Capacitor Voltage ConvertersMAX1044/ICL766019-4667; Rev 1; 7/94Switched-Capacitor Voltage Converters_______________
MAX1044ESA+ ,Switched-Capacitor Voltage ConvertersApplicationsMAX1044EPA -40°C to +85°C 8 Plastic DIP-5V Supply from +5V Logic SupplyOrdering Informa ..
MAX1044ESA+T ,Switched-Capacitor Voltage ConvertersGeneral Description ________
M68AF127BM55MC6U-M68AF127BM70B6U-M68AF127BM70MC1U-M68AF127BM70N6
1 MBIT (128K X8) 5.0V ASYNCHRONOUS SRAM
M68AF127B1Mbit (128K x8), 5V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 4.5 to 5.5V 128K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
Figure 1. Packages
M68AF127B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . .11
Figure 11.Chip Enable Controlled, Standby Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 12.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 14.E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 15.E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . .16
Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 16.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . .17
Figure 17.PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . .18
Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . .18
Figure 18.TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline. . . . . . . .19
M68AF127BTable 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 19.TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline . . . . . . . . . . .20
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data . . .20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
M68AF127B
SUMMARY DESCRIPTIONThe M68AF127B is a 1Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
4.5 to 5.5V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AF127B is available in SO32, PDIP32,
TSOP32 (8x13.4mm) and TSOP32 (8x20mm)
packages.
Figure 2. Logic Diagram Table 1. Signal Names
M68AF127B
Figure 5. TSOP Connections
M68AF127B
M68AF127B
OPERATIONThe M68AF127B has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E1 = High),
or Chip Select is asserted (E2 = Low). An Output
Enable (G) signal provides a high-speed, tri-state
control, allowing fast read/write cycles to be
achieved with the common I/O data bus. Opera-
tional modes are determined by device control in-
puts W and E1 as summarized in the Operating
Modes table (Table 2).
Read ModeThe M68AF127B is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, Chip Enable (E1) is asserted and Chip Select
(E2) is de-asserted. This provides access to data
from eight of the 1,048,576 locations in the static
memory array, specified by the 17 address inputs.
Valid data will be available at the eight output pins
within tAVQV after the last stable address, provid-
ing G is Low and E1 is Low. If Chip Enable or Out-
put Enable access times are not met, data access
will be measured from the limiting parameter
(tELQV or tGLQV) rather than the address. Data out
may be indeterminate at tELQX and tGLQX, but data
lines will always be valid at tAVQV.
Write ModeThe M68AF127B is in the Write mode whenever
the W and E1 pins are Low and the E2 pin is High.
Either the Chip Enable input (E1) or the Write En-
able input (W) must be de-asserted during Ad-
dress transitions for subsequent write cycles.
Write begins with the concurrence of E1 being ac-
tive with W low. Therefore, address setup time is
referenced to Write Enable and Chip Enable as
tAVWL and tAVEH, respectively, and is determined
by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E1, or W.
If the Output is enabled (E1 = Low, E2 = High and
G = Low), then W will return the outputs to high im-
pedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for tDVWH before
the rising edge of Write Enable, or for tDVEH before
the rising edge of E1, whichever occurs first, and
remain valid for tWHDX or tEHDX.
Table 2. Operating ModesNote: X = VIH or VIL.
M68AF127B
MAXIMUM RATINGStressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 3. Absolute Maximum RatingsNote:1. One output at a time, not to exceed 1 second duration. Up to a maximum operating VCC of 6.0V only.
M68AF127B
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit
M68AF127B
Table 5. CapacitanceNote:1. Sampled only, not 100% tested. At TA = 25°C, f = 1MHz, VCC = 3.0V.
Table 6. DC Characteristics Note:1. Average AC current, cycling at tAVAV minimum. E1 = VIL, E2 = VIH, VIN = VIH or VIL. E1 ≤ 0.2V or E2 ≥ VCC –0.2V, VIN ≤ 0.2V or VIN ≥ VCC –0.2V. Output disabled.
M68AF127B
Figure 9. Address Controlled, Read Mode AC WaveformsNote: E1 = Low, E2 = High, G = Low, W = High.
Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC WaveformsNote: Write Enable (W) = High.
M68AF127B
Figure 11. Chip Enable Controlled, Standby Mode AC Waveforms
