M59DR016C ,16 MBIT (1MB X16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYLogic Diagram■ DUAL BANK OPERATIONS– Read within one Bank while Program orErase within the other– N ..
M59DR032A120ZB6T ,32 MBIT (2MB X16, DUAL BANK) LOW VOLTAGE FLASH MEMORYLogic Diagram■ DUAL BANK OPERATIONS– Read within one Bank while Program orErase within the other– N ..
M59DR032EA10ZB6 ,32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYAbsolute Maximum Ratings . . . . . . . 20DC and AC PARAMETERS . 21Table 14. Operating an ..
M59DR032EA10ZB6 ,32 MBIT (2MB X 16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORYLogic Diagram . . 5Table 1. Signal Names . . . 5Figure 3. TFBGA Connections (Top view ..
M59MR032C120GC6T ,32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash MemoryLogic Diagram– Parameter Blocks (Top or Bottom location) ■ DUAL BANK OPERATIONS– Read within one Ba ..
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MA02303GJ-R7 ,2200-2600 MHz, RF power amplifier IC for 2.4 GHz ISM
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M59DR016C
16 MBIT (1MB X16, DUAL BANK, PAGE) 1.8V SUPPLY FLASH MEMORY
1/37
PRODUCT PREVIEWMarch 2001
M59DR016C
M59DR016D16 Mbit (1Mb x16, Dual Bank, Page)
1.8V Supply Flash Memory SUPPLY VOLTAGE
–VDD = VDDQ = 1.65V to 2.2V for Program,
Erase and Read
–VPP = 12V for fast Program (optional) ASYNCHRONOUS PAGE MODE READ Page Width: 4 words Page Access: 35ns Random Access: 100ns PROGRAMMING TIME 10μs by Word typical Double Word Programming Option MEMORY BLOCKS Dual Bank Memory Array: 4 Mbit - 12 Mbit Parameter Blocks (Top or Bottom location) DUAL BANK OPERATIONS Read within one Bank while Program or
Erase within the other No delay between Read and Write operations BLOCK PROTECTION/UNPROTECTION All Blocks protected at Power Up Any combination of Blocks can be protected COMMON FLASH INTERFACE (CFI) 64 bit SECURITY CODE ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M59DR016C: 2293h Bottom Device Code, M59DR016D: 2294h
M59DR016C, M59DR016D
Table 1. Signal Names
DESCRIPTIONThe M59DR016 is a 16 Mbit non-volatile Flash
memory that may be erased electrically at block
level and programmed in-system on a Word-by-
Word basis using a 1.65V to 2.2V VDD supply for
the circuitry. For Program and Erase operations
the necessary high voltages are generated inter-
nally. The device supports asynchronous page
mode from all the blocks of the memory array.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against pro-
gramming and erase at Power Up. Blocks can be
unprotected to make changes in the application
and then reprotected.
Instructions for Read/Reset, Auto Select, Write
Configuration Register, Programming, Block
Erase, Bank Erase, Erase Suspend, Erase Re-
sume, Block Protect, Block Unprotect, Block Lock-
ing, CFI Query, are written to the memory through
a Command Interface using standard micropro-
cessor write timings.
The device is offered in TFBGA48 (0.75 mm pitch)
packages and it is supplied with all the bits erased
(set to ‘1’).
3/37
M59DR016C, M59DR016D
OrganizationThe M59DR016 is organized as 1Mb x16 bits. A0-
A19 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory control is provided by
Chip Enable E, Output Enable G and Write Enable
W inputs.
Reset RP is used to reset all the memory circuitry
and to set the chip in power down mode if this
function is enabled by a proper setting of the Con-
figuration Register. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides error bit
to indicate the state of the P/E.C operations.
Memory BlocksThe device features asymmetrically blocked archi-
tecture. M59DR016 has an array of 39 blocks and
is divided into two banks A and B, providing Dual
Bank operations. While programming or erasing in
Bank A, read operations are possible into Bank B
or vice versa. The memory also features an erase
suspend allowing to read or program in another
block within the same bank. Once suspended the
erase can be resumed. The Bank Size and Sector-
ization are summarized in Table 7. Parameter
Blocks are located at the top of the memory ad-
dress space for the M59DR016C, and at the bot-
tom for the M59DR016D. The memory maps are
shown in Tables 3, 4, 5 and 6.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additional data
security. All blocks are protected at Power Up. In-
structions are provided to protect or unprotect any
block in the application. A second register locks
the protection status while WP is low (see Block
Locking description). The Reset command does
not affect the configuration of unprotected blocks
and the Configuration Register status.
Table 2. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Depends on range. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
M59DR016C, M59DR016D
Table 3. Bank A, Top Boot Block Addresses
M59DR016C
Table 4. Bank B, Top Boot Block Addresses
M59DR016C
Table 5. Bank B, Bottom Boot Block Addresses
M59DR016D
Table 6. Bank A, Bottom Boot Block Addresses
M59DR016D
5/37
M59DR016C, M59DR016D
SIGNAL DESCRIPTIONSSee Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs
for the memory array are latched during a write op-
eration on the falling edge of Chip Enable E or
Write Enable W, whichever occurs last.
Data Input/Output (DQ0-DQ15). The Input is
data to be programmed in the memory array or a
command to be written to the Command Interface
(C.I.) Both input data and commands are latched
on the rising edge of Write Enable W. The Ouput
is data from the Memory Array, the Common Flash
Interface, the Electronic Signature Manufacturer
or Device codes, the Block Protection status, the
Configuration Register status or the Status Regis-
ter Data Polling bit DQ7, the Toggle Bits DQ6 and
DQ2, the Error bit DQ5. The data bus is high im-
pedance when the chip is deselected, Output En-
able G is at VIH, or RP is at VIL.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at VIH deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at VIL.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is at VIH the outputs are High im-
pedance.
Write Enable (W). This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP). This input gives an addition-
al hardware protection level against program or
erase when pulled at VIL, as described in the Block
Lock instruction description.
Reset/Power Down Input (RP). The RP input
provides hardware reset of the memory (without
affecting the Configuration Register status), and/
or Power Down functions, depending on the Con-
figuration Register status. Reset/Power Down of
the memory is achieved by pulling RP to VIL for at
least tPLPH. When the reset pulse is given, if the
memory is in Read, Erase Suspend Read or
Standby, it will output new valid data in tPHQ7V1 af-
ter the rising edge of RP. If the memory is in Erase
or Program modes, the operation will be aborted
and the reset recovery will take a maximum ot
tPLQ7V. The memory will recover from Power
Down (when enabled) in tPHQ7V2 after the rising
edge of RP. See Tables 25, 26 and Figure 9.
VDD and VDDQ Supply Voltage (1.65V to 2.2V).The main power supply for all operations (Read,
Program and Erase). VDD and VDDQ must be at
the same voltage.
VPP Programming Voltage (11.4V to 12.6V). Used
to provide high voltage for fast factory program-
ming. High voltage on VPP pin is required to use
the Double Word Program instruction. It is also
possible to perform word program or erase instruc-
tions with VPP pin grounded.
VSS Ground. VSS is the reference for all the volt-
age measurements.
DEVICE OPERATIONSThe following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Dis-
able, Standby, Reset/Power Down and Block
Locking. See Table 8.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is per-
formed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asyncronous read
cycles (Random Read). Both Chip Enable E and
Output Enable G must be at VIL in order to read the
output of the memory.
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch Input
Data to be programmed. A write operation is initi-
ated when Chip Enable E and Write Enable W are
at VIL with Output Enable G at VIH. Addresses are
latched on the falling edge of W or E whichever oc-
curs last. Commands and Input Data are latched
on the rising edge of W or E whichever occurs first.
Noise pulses of less than 5ns typical on E, W and
G signals do not start a write cycle.
Table 7. Bank Size and Sectorization
M59DR016C, M59DR016D
Table 8. User Bus Operations (1)Note:1. X = Don’t care.
Table 9. Read Electronic Signature (AS and Read CFI instructions)
Table 10. Read Block Protection (AS and Read CFI instructions)
Table 11. Read Configuration Register (AS and Read CFI instructions)
Automatic Standby. When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus.
Power Down. The memory is in Power Down
when the Configuration Register is set for Power
Down and RP is at VIL. The power consumption is
reduced to the Power Down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Block Locking. Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to VIL (see Block Lock instruction).
Dual Bank Operations. The Dual Bank allows to
read data from one bank of memory while a pro-
gram or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an ad-
dress within the bank being modified.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby. The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The pow-
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
7/37
M59DR016C, M59DR016D
INSTRUCTIONS AND COMMANDSSeventeen instructions are defined (see Table
14), and the internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits can be read at any time, dur-
ing programming or erase, to monitor the progress
of the operation.
Instructions, made up of one or more commands
written in cycles, can be given to the Program/
Erase Controller through a Command Interface
(C.I.). The C.I. latches commands written to the
memory. Commands are made of address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followed by an input
command or a confirmation command. The Coded
Sequence consists of writing the data AAh at the
address 555h during the first cycle and the data
55h at the address 2AAh during the second cycle.
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all in-
structions (see Table 14). The third cycle inputs
the instruction set-up command. Subsequent cy-
cles output the addressed data, Electronic Signa-
ture, Block Protection, Configuration Register
Status or CFI Query for Read operations. In order
to give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. For a Program instruction, the
fourth command cycle inputs the address and data
to be programmed. For a Double Word Program-
ming instruction, the fourth and fifth command cy-
cles input the address and data to be
programmed. For a Block Erase and Bank Erase
instructions, the fourth and fifth cycles input a fur-
ther Coded Sequence before the Erase confirm
command on the sixth cycle. Any combination of
blocks of the same memory bank can be erased.
Erasure of a memory block may be suspended, in
order to read data from another block or to pro-
gram data in another block, and then resumed.
When power is first applied the command interface
is reset to Read Array.
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to ensure maximum
data security.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded Cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read.
CFI Query (RCFI) Instruction. Common Flash
Interface Query mode is entered writing 98h at ad-
dress 55h. The CFI data structure gives informa-
tion on the device, such as the sectorization, the
command set and some electrical specifications.
Tables 15, 19, 20 and 21 show the addresses
used to retrieve each data. The CFI data structure
contains also a security area; in this section, a 64
bit unique security number is written, starting at
address 80h. This area can be accessed only in
read mode by the final user and there are no ways
of changing the code after it has been written by
ST. Write a read instruction (RD) to return to Read
mode.
Table 12. Commands
M59DR016C, M59DR016D
Auto Select (AS) Instruction. This instruction
uses two Coded Cycles followed by one write cy-
cle giving the command 90h to address 555h for
command set-up. A subsequent read will output
the Manufacturer or the Device Code (Electronic
Signature), the Block Protection status or the Con-
figuration Register status depending on the levels
of A0 and A1 (see Tables 9, 10 and 11). A7-A2
must be at VIL, while other address input are ig-
nored. The bank address is don’t care for this in-
struction. The Electronic Signature can be read
from the memory allowing programming equip-
ment or applications to automatically match their
interface to the characteristics of M59DR016. The
Manufacturer Code is output when the address
lines A0 and A1 are at VIL, the Device Code is out-
put when A0 is at VIH with A1 at VIL.
The codes are output on DQ0-DQ7 with DQ8-
DQ15 at 00h. The AS instruction also allows the
access to the Block Protection Status. After giving
the AS instruction, A0 is set to VIL with A1 at VIH,
while A12-A19 define the address of the block to
be verified. A read in these conditions will output a
01h if the block is protected and a 00h if the block
is not protected.
The AS Instruction finally allows the access to the
Configuration Register status if both A0 and A1
are set to VIH. If DQ10 is '0' only the Reset function
is active as RP is set to VIL (default at power-up).
If DQ10 is '1' both the Reset and the Power Down
functions will be achieved by pulling RP to VIL. The
other bits of the Configuration Register are re-
served and must be ignored. A reset command
puts the device in read array mode.
Write Configuration Register (CR) Instruc-
tion. This instruction uses two Coded Cycles fol-
lowed by one write cycle giving the command 60h
to address 555h. A further write cycle giving the
command 03h writes the contents of address bits
A0-A15 to the 16 bits configuration register. Bits
written by inputs A0-A9 and A11-A15 are reserved
for future use. Address input A10 defines the sta-
tus of the Reset/Power Down functions. It must be
set to VIL to enable only the Reset function and to
VIH to enable also the Power Down function. At
Power Up all the Configuration Register bits are
reset to '0'.
Enter Bypass Mode (EBY) Instruction. This in-
struction uses the two Coded cycles followed by
one write cycle giving the command 20h to ad-
dress 555h for mode set-up. Once in Bypass
mode, the device will accept the Exit Bypass
(XBY) and Program or Double Word Program in
Bypass mode (PGBY, DPGBY) commands. The
Bypass mode allows to reduce the overall pro-
gramming time when large memory arrays need to
be programmed.
Exit Bypass Mode (XBY) Instruction. This in-
struction uses two write cycles. The first inputs to
the memory the command 90h and the second in-
puts the Exit Bypass mode confirm (00h). After the
XBY instruction, the device resets to Read Memo-
ry Array mode.
Program in Bypass Mode (PGBY) Instruc-
tion. This instruction uses two write cycles. The
Program command A0h is written to any Address
on the first cycle and the second write cycle latch-
es the Address on the falling edge of W or E and
the Data to be written on the rising edge and starts
the P/E.C. Read operations within the same bank
output the Status Register bits after the program-
ming has started. Memory programming is made
only by writing '0' in place of '1'. Status bits DQ6
and DQ7 determine if programming is on-going
and DQ5 allows verification of any possible error.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write operation latches the
Address and the Data to be written and starts the
P/E.C. Read operations within the same bank out-
put the Status Register bits after the programming
has started. Memory programming is made only
by writing '0' in place of '1'. Status bits DQ6 and
DQ7 determine if programming is on-going and
DQ5 allows verification of any possible error. Pro-
gramming at an address not in blocks being
erased is also possible during erase suspend.
Double Word Program (DPG) Instruction. This
feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel. High voltage (11.4V to 12.6V) on VPP
pin is required. This instruction uses five write cy-
cles. The double word program command 40h is
written to address 555h on the third cycle after two
Coded Cycles. A fourth write cycle latches the ad-
dress and data to be written to the first location. A
fifth write cycle latches the new data to be written
to the second location and starts the P/E.C.. Note
that the two locations must have the same address
except for the address bit A0. The Double Word
Program can be executed in Bypass mode (DPG-
BY) to skip the two coded cycles at the beginning
of each command.
9/37
M59DR016C, M59DR016D
Block Protect (BP), Block Unprotect (BU),
Block Lock (BL) Instructions. All blocks are
protected at power-up. Each block of the array has
two levels of protection against program or erase
operation. The first level is set by the Block Protect
instruction; a protected block cannot be pro-
grammed or erased until a Block Unprotect in-
struction is given for that block. A second level of
protection is set by the Block Lock instruction, and
requires the use of the WP pin, according to the
following scheme: when WP is at VIH, the Lock status is overridden
and all blocks can be protected or unprotected; when WP is at VIL, Lock status is enabled; the
locked blocks are protected, regardless of their
previous protect state, and protection status
cannot be changed. Blocks that are not locked
can still change their protection status, and pro-
gram or erase accordingly; the lock status is cleared for all blocks at power
up; once a block has been locked state can be
cleared only with a reset command. The protec-
tion and lock status can be monitored for each
block using the Autoselect (AS) instruction. Pro-
tected blocks will output a ‘1’ on DQ0 and locked
blocks will output a ‘1’ on DQ1.
Refer to Table 13 for a list of the protection states.
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles and an address within the block to be
erased is given and latched into the memory.
Table 13. Protection States (1)Note:1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by
DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Autoselect instruction with A1 = VIH and A0 = VIL. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed
its logic value. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. All blocks must belong to the same
bank of memory; if a new block belonging to the
other bank is given, the operation is aborted. The
erase will start after an erase timeout period of
100μs. Thus, additional Erase Confirm commands
for other blocks must be given within this delay.
The input of a new Erase Confirm command will
restart the timeout period. The status of the inter-
nal timer can be monitored through the level of
DQ3, if DQ3 is '0' the Block Erase Command has
been given and the timeout is running, if DQ3 is '1',
the timeout has expired and the P/E.C. is erasing
the Block(s). If the second command given is not
an erase confirm or if the Coded cycles are wrong,
the instruction aborts, and the device is reset to
Read Array. It is not necessary to program the
block with 00h as the P/E.C. will do this automati-
cally before erasing to FFh. Read operations with-
in the same bank, after the sixth rising edge of W
or E, output the status register bits.
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction; the Read/Reset RD instruction is ac-
cepted during the 100μs time-out period. Data
Polling bit DQ7 returns '0' while the erasure is in
progress and '1' when it has completed. The Tog-
gle bit DQ6 toggles during the erase operation,
and stops when erase is completed.
After completion the Status Register bit DQ5 re-
turns '1' if there has been an erase failure. In such
a situation, the Toggle bit DQ2 can be used to de-
termine which block is not correctly erased. In the
case of erase failure, a Read/Reset RD instruction
is necessary in order to reset the P/E.C.
M59DR016C, M59DR016D
Bank Erase (BKE) Instruction. This instruction
uses six write cycles and is used to erase all the
blocks belonging to the selected bank. The Erase
Set-up command 80h is written to address 555h
on the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10h is similarly
written on the sixth cycle after another two Coded
cycles at an address within the selected bank. If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts and the device is reset to Read Array.
It is not necessary to program the array with 00h
first as the P/E.C. will automatically do this before
erasing it to FFh. Read operations within the same
bank after the sixth rising edge of W or E output
the Status Register bits. During the execution of
the erase by the P/E.C., Data Polling bit DQ7 re-
turns ’0’, then ’1’ on completion. The Toggle bit
DQ6 toggles during erase operation and stops
when erase is completed. After completion the
Status Register bit DQ5 returns ’1’ if there has
been an Erase Failure.
Erase Suspend (ES) Instruction. In a dual bank
memory the Erase Suspend instruction is used to
read data within the bank where erase is in
progress. It is also possible to program data in
blocks not being erased.
The Erase Suspend instruction consists of writing
the command B0h without any specific address.
No Coded Cycles are required. Erase suspend is
accepted only during the Block Erase instruction
execution. The Toggle bit DQ6 stops toggling
when the P/E.C. is suspended within 15μs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be set to
Read Memory Array mode. When erase is sus-
pended, a Read from blocks being erased will out-
put DQ2 toggling and DQ6 at '1'. A Read from a
block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in DQ6 toggling when the data
is being programmed.
Erase Resume (ER) Instruction. If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at an address within the bank be-
ing erased and without any Coded Cycle.
11/37
M59DR016C, M59DR016D
Table 14. Instructions (1,2)
M59DR016C, M59DR016DNote:1. Commands not interpreted in this table will default to read array mode. For Coded cycles address inputs A11-A19 are don’t care. X = Don’t Care. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
mand cycles. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. Program Address 1 and Program Address 2 must be consecutive addresses differing only for address bit A0. High voltage on VPP (11.4V to 12.6V) is required for the proper execution of the Double Word Program instruction.
13/37
M59DR016C, M59DR016D
Table 15. Status Register Bits (1)Note:1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. In case of double word program DQ7 refers to the last word input.
M59DR016C, M59DR016D
STATUS REGISTER BITSP/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 bits. Any read attempt within
the Bank being modified and during Program or
Erase command execution will automatically out-
put these five Status Register bits. The P/E.C. au-
tomatically sets bits DQ2, DQ5, DQ6 and DQ7.
Other bits (DQ0, DQ1 and DQ4) are reserved for
future use and should be masked (see Tables 15
and 16). Read attemps within the bank not being
modified will output array data.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7. In
case of a double word program operation, the
complement is done on DQ7 of the last word writ-
ten to the command interface, i.e. the data written
in the fifth cycle. During Erase operation, it outputs
a ’0’. After completion of the operation, DQ7 will
output the bit last programmed or a ’1’ after eras-
ing. Data Polling is valid and only effective during
P/E.C. operation, that is after the fourth W pulse
for programming or after the sixth W pulse for
erase. It must be performed at the address being
programmed or at an address within the block be-
ing erased. See Figure 12 for the Data Polling
flowchart and Figure 10 for the Data Polling wave-
forms. DQ7 will also flag the Erase Suspend mode
by switching from ’0’ to ’1’ at the start of the Erase
Suspend. In order to monitor DQ7 in the Erase
Suspend mode an address within a block being
erased must be provided. For a Read Operation in
Table 16. Polling and Toggle BitsSuspend mode, DQ7 will output ’1’ if the read is at-
tempted on a block being erased and the data val-
ue on other blocks. During Program operation in
Erase Suspend Mode, DQ7 will have the same be-
haviour as in the normal program execution out-
side of the suspend mode.
Toggle Bit (DQ6). When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or E when G is at VIL. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammed or a ’1’ after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. DQ6 will be set to ’1’ if a
Read operation is attempted on an Erase Suspend
block. When erase is suspended DQ6 will toggle
during programming operations in a block different
from the block in Erase Suspend. Either E or G
toggling will cause DQ6 to toggle. See Figure 13
for Toggle Bit flowchart and Figure 11 for Toggle
Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. During Erase Sus-
pend a read from a block being erased will cause
DQ2 to toggle. A read from a block not being
erased will output data. DQ2 will be set to ’1’ during
program operation and to ‘0’ in Erase operation.
After erase completion and if the error bit DQ5 is
set to '1', DQ2 will toggle if the faulty block is ad-
dressed.
Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming or block
erase, that results in invalid data in the memory
block. In case of an error in block erase or pro-
gram, the block in which the error occurred or to
which the programmed data belongs, must be dis-
carded. Other Blocks may still be used. The error
bit resets after a Read/Reset (RD) instruction. In
case of success of Program or Erase, the error bit
will be set to '0'.
Erase Timer Bit (DQ3). This bit is set to ‘0’ by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, DQ3 returns to ‘1’, in the range
of 80μs to 120μs.
15/37
M59DR016C, M59DR016D
Table 17. Program, Erase Times and Program, Erase Endurance Cycles(TA = 0 to 70°C; VDD = VDDQ = 1.65V to 2.2V, VPP = VDD unless otherwise specified)
Note:1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better. Excludes the time needed to execute the sequence for program instruction. Same timing value if VPP = 12V.
POWER CONSUMPTION
Power DownThe memory provides Reset/Power Down control
input RP. The Power Down function can be acti-
vated only if the relevant Configuration Register bit
is set to ’1’. In this case, when the RP signal is
pulled at VSS the supply current drops to typically
ICC2 (see Table 22), the memory is deselected and
the outputs are in high impedance.If RP is pulled
to VSS during a Program or Erase operation, this
operation is aborted in tPLQ7V and the memory
content is no longer valid (see Reset/Power Down
input description).
Power UpThe memory Command Interface is reset on Pow-
er Up to Read Array. Either E or W must be tied to
VIH during Power Up to allow maximum security
and the possibility to write a command on the first
rising edge of W.
Supply RailsNormal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the VDD rails decoupled with a 0.1μF capac-
itor close to the VDD, VDDQ and VSS pins. The PCB
trace widths should be sufficient to carry the re-
quired VDD program and erase currents.
M59DR016C, M59DR016D
Table 18. Query Structure OverviewNote: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections
detailled in Tables 19, 20 and 21. Query data are always presented on the lowest order data outputs.
Table 19. CFI Query Identification StringNote: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
COMMON FLASH INTERFACE (CFI)The Common Flash Interface (CFI) specification is
a JEDEC approved, standardised data structure
that can be read from the Flash memory device.
CFI allows a system software to query the flash
device to determine various electrical and timing
parameters, density information and functions
supported by the device. CFI allows the system to
easily interface to the Flash memory, to learn
about its features and parameters, enabling the
software to configure itself when necessary.
Tables 18, 19, 20 and 21 show the address used
to retrieve each data.
The CFI data structure gives information on the
device, such as the sectorization, the command
set and some electrical specifications. Tables 18,
19, 20 and 21 show the addresses used to retrieve
each data. The CFI data structure contains also a
security area; in this section, a 64 bit unique secu-
rity number is written, starting at address 81h. This
area can be accessed only in read mode and there
are no ways of changing the code after it has been
written by ST. Write a read instruction to return to
Read mode. Refer to the CFI Query instruction to
understand how the M59DR016 enters the CFI
Query mode.
17/37
M59DR016C, M59DR016D
Table 20. CFI Query System Interface Information
M59DR016C, M59DR016D
Table 21. Device Geometry Definition
19/37
M59DR016C, M59DR016D
Table 22. AC Measurement Conditions
Table 23. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Note:1. Sampled only, not 100% tested.
