M58LW128A ,128 MBIT (8MB X16 OR 4MB X32, UNIFORM BLOCK, BURST) 3V SUPPLY FLASH MEMORIESLogic Diagram . 7Table 1. Signal Names . . 7Figure 3. TSOP56 Connections . . . ..
M58MR032C100ZC6T ,32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash MemoryLogic Diagram– Parameter Blocks (Top or Bottom location) ■ DUAL OPERATIONS– Read within one Bank wh ..
M58WR032FB60ZB6 ,32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash MemoryLogic Diagram . . 8Table 1. Signal Names . . 8Figure 3. VFBGA Connections (Top view t ..
M58WR032FB60ZB6 ,32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash MemoryFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Package–V = 1.7V to 2V for Program, Erase and DDRead–V = ..
M58WR032KU70ZA6U , 16-, 32- and 64-Mbit (x 16, Mux I/O, Multiple Bank, Burst) 1.8 V supply Flash memories
M58WR032QT70ZB6F , 16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories
M95320-WMN6TP ,64KBIT AND 32KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95512-RDW6P , 512 Kbit Serial SPI bus EEPROMtm with high speed clock
M95512-WDW6TP ,512 Kbit SPI bus EEPROM with high-speed clock
M95640-MN3 ,64/32/16/8 KBIT SERIAL SPI EEPROM WITH HIGH SPEED CLOCK AND POSITIVE CLOCK STROBEFEATURES SUMMARY■ Compatible with SPI Bus Serial Interface Figure 1. Packages(Positive Clock SPI Mo ..
M95640-WDL6T ,64KBIT AND 32KBIT SERIAL SPI BUS EEPROM WITH HIGH SPEED CLOCKFEATURES . . . . 9Power-up . . . . . 9Power On Reset: VCC Lock-Out Write Protect ..
M95640-WDW6P ,32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed ClockLogic Diagram . . 5Figure 3. DIP and SO Connections . . 5Figure 4. TSSOP14 Connections ..
M58LW128A
128 MBIT (8MB X16 OR 4MB X32, UNIFORM BLOCK, BURST) 3V SUPPLY FLASH MEMORIES
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PRELIMINARY DATAFebruary 2003
M58LW128A
M58LW128B128 Mbit (8Mb x16 or 4Mb x32, Uniform Block, Burst)
3V Supply Flash Memories
FEATURES SUMMARY WIDE DATA BUS for HIGH BANDWIDTH M58LW128A: x16 M58LW128B: x16/x32 SUPPLY VOLTAGE
–VDD = 2.7 to 3.6V core supply voltage for Pro-
gram, Erase and Read operations
–VDDQ = 1.8 to VDD for I/O Buffers SYNCHRONOUS/ASYNCHRONOUS READ Synchronous Burst read Pipelined Synchronous Burst Read Asynchronous Random Read Asynchronous Address Latch Controlled
Read Page Read ACCESS TIME Synchronous Burst Read up to 66MHz Asynchronous Page Mode Read 150/25ns Random Read 150ns PROGRAMMING TIME 16 Word or 8 Double-Word Write Buffer
–12μs Word effective programming time 128 UNIFORM 64 KWord MEMORY BLOCKS BLOCK PROTECTION/ UNPROTECTION PROGRAM and ERASE SUSPEND OTP SECURITY AREA COMMON FLASH INTERFACE 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code M58LW128A: 8818h Device Code M58LW128B: 8819h
Figure 1. Packages
M58LW128A, M58LW128B
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. TBGA64 Connections for M58LW128A (Top view through package) . . . . . . . . . . . . . . . 9
Figure 5. TBGA80 Connections for M58LW128B (Top view through package) . . . . . . . . . . . . . . 10
Figure 6. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Address Inputs (A1-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Word Organization (WORD).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Program/Erase Enable (VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Input/Output Supply Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Ground (VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Ground (VSSQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 2. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Synchronous Pipelined Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 3. Synchronous Burst Read Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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M58LW128A, M58LW128BTable 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read . . . . . . . . . . . . . 17
Figure 7. Synchronous Burst Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Example Synchronous Pipelined Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Example Burst Address Advance and Burst Abort operations. . . . . . . . . . . . . . . . . . . . 19
Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
X-Latency Bits (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Latch Enable Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 5. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Burst Type Definition (x16 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Burst Type Definition (x32 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Burst Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 28
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
VPP Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M58LW128A, M58LW128B
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 13. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Table 14. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 36
Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 36
Figure 14. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 38
Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 38
Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . 40
Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 40
Table 21. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 19. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 43
Table 22. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 21. Reset, Power-Down and Power-Up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 23. Reset, Power-Down and Power-Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 46
Table 24. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 46
Figure 23. TBGA64 - 10x13mm - 8 x 8 ball array, 1mm pitch, Package Outline. . . . . . . . . . . . . . 47
Table 25. TBGA64 - 10x13mm - 8 x 8 ball array, 1 mm pitch, Package Mechanical Data . . . . . . 47
Figure 24. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Outline. . . . . . . . . . . . . 48
Table 26. TBGA80 - 10x13mm - 8 x 10 ball array, 1mm pitch, Package Mechanical Data. . . . . . 48
PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 28. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5/65
M58LW128A, M58LW128BTable 30. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 25. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 57
Figure 26. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 58
Figure 27. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 28. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 60
Figure 29. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 61
Figure 30. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 62
Figure 31. Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . 63
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64Table 35. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
M58LW128A, M58LW128B
SUMMARY DESCRIPTIONM58LW128 is a 128 Mbit (8Mb x16 or 4Mb x32)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7V to 3.6V)
core supply. On power-up the memory defaults to
Read mode with an asynchronous bus where it
can be read in the same way as a non-burst Flash
memory.
The memory is divided into 128 blocks of 1Mbit
that can be erased independently so it is possible
to preserve valid data while old data is erased.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to pro-
gram up to 16 Words (or 8 Double Words) in par-
allel, both speeding up the programming and
freeing up the microprocessor to perform other
work. The minimum buffer size for a program op-
eration is an 8 Word (or 4 Double Word) page. A
page can only be programmed once between
Erase operations.
Erase can be suspended in order to perform either
read or program in any other block and then re-
sumed. Program can be suspended to read data in
any other block and then resumed. Each block can
be programmed and erased over 100,000 cycles.
Individual block protection against program or
erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All program or erase opera-
tions are blocked when the Program Erase Enable
input Vpp is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in Power-Down mode. It can also be used to
temporarily disable the protection mechanism.
In asynchronous mode Chip Enable, Output En-
able and Write Enable signals control the bus op-
eration of the memory. An Address Latch input can
be used to latch addresses in Latch Controlled
mode. Together they allow simple, yet powerful,
connection to most microprocessors, often without
additional logic.
In synchronous mode all Bus Read operations are
synchronous with the Clock. Chip Enable and Out-
put Enable select the Bus Read operation; the ad-
dress is Latched using the Latch Enable inputs
and the address is advanced using Burst Address
Advance. The signals are compatible with most
microprocessor burst interfaces.
A One Time Programmable (OTP) area is included
for security purposes. Either 512 Words (x16 Bus
Width) or 512 Double-Words (x32 Bus Width) is
available in the OTP area. The process of reading
from and writing to the OTP area is not published
for security purposes; contact STMicroelectronics
for details on how to use the OTP area.
The memory is offered in various packages. The
M58LW128A is available in TSOP56 (14 x 20 mm)
and TBGA64 (1mm pitch). The M58LW128B is
available in TBGA80 (1mm pitch).
7/65
M58LW128A, M58LW128B
Figure 2. Logic Diagram Note:1. M58LW128B only.
Table 1. Signal Names
M58LW128A, M58LW128B
9/65
M58LW128A, M58LW128B
M58LW128A, M58LW128B
Figure 5. TBGA80 Connections for M58LW128B (Top view through package)
11/65
M58LW128A, M58LW128B
Figure 6. Block AddressesNote: Also see Appendix A, Table 28 for a full listing of the Block Addresses
SIGNAL DESCRIPTIONSSee Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A1-A23). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable must be low when selecting the ad-
dresses.
The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a write operation. The ad-
dress latch is transparent when Latch Enable is
low, VIL. The address is internally latched in a pro-
gram or erase operation.
With a x32 Bus Width, WORD = VIH, Address Input
A1 is ignored; the Least Significant Word is output
on DQ0-DQ15 and the Most Significant Word is
output on DQ16-DQ31. With a x16 Bus Width,
WORD = VIL, the Least Significant Word is output
on DQ0-DQ15 when A1 is low, VIL, and the Most
Significant Word is output on DQ0-DQ15 when A1
is high, VIH.
Data Inputs/Outputs (DQ0-DQ31). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a Program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
low, VIL, the data bus outputs data from the mem-
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the chip is deselected, Output Enable
is High, VIH, or the Reset/Power-Down signal is
Low, VIL. When the Program/Erase Controller is
active the Ready/Busy status is given on DQ7
while DQ0-DQ6 and DQ8-DQ31 are high imped-
ance.
With a x16 Bus Width, WORD = VIL, DQ16-DQ31
are not used and are high impedance.
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
VIH deselects the memory and reduces the power
consumption to the Standby level, IDD1.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at VIH
M58LW128A, M58LW128Bthe outputs are high impedance. Output Enable,
G, can be used to inhibit the data output during a
burst read operation.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The Reset/Power-
Down pin can be used to apply a Hardware Reset
to the memory or to temporarily unprotect all
blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, VIL, for at least tPLPH. When
Reset/Power-Down is Low, VIL, the Status Regis-
ter information is cleared and the current is re-
duced to IDD2 (refer to Table 16, DC
Characteristics). The device is deselected and
outputs are high impedance. If Reset/Power-
Down goes low, VIL,during a Block Erase, a Write
to Buffer and Program or a Block Protect/Unpro-
tect the operation is aborted and the data may be
corrupted. In this case the Ready/Busy pin stays
low, VIL, for a maximum timing of tPLPH + tPHRH.
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read and Bus Write
operations after tRHEL. Note that Ready/Busy does
not fall during a reset, see Ready/Busy Output
section.
During power-up Reset/Power-Down must be held
Low, VIL. Furthermore it must stay low for tVDHPH
after the Supply Voltage inputs become stable.
The device will then be configured in Asynchro-
nous Random Read mode.
See Table 23 and Figure 21, Reset, Power-Down
and Power-up Characteristics, for more details.
Holding RP at VHH will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing a pro-
gram or erase operation, the memory may output
the Status Register information instead of being
initialized to the default Asynchronous Random
Read.
Latch Enable (L). The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L. In synchronous bus oper-
ations the address is latched on the active edge of
the Clock when Latch Enable is Low, VIL. Once
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
Enable is Low, VIL, the latch is transparent.
Clock (K). The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
low, VIL, or on the rising edge of Latch Enable,
whichever occurs first.
During Asynchronous Bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during synchro-
nous bus operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X- or Y-
latency time has expired. If Burst Address Ad-
vance is Low, VIL, the internal address counter ad-
vances. If Burst Address Advance is High, VIH, the
internal address counter does not change; the
same data remains on the Data Inputs/Outputs
and Burst Address Advance is not sampled until
the Y-latency expires.
The Burst Address Advance, B, may be tied to VIL.
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
one cycle before. Valid Data Ready Low, VOL, in-
dicates that the data is not, or will not be valid. Val-
id Data Ready in a high-impedance state indicates
that valid data is or will be available.
Unless the Burst Length is set to Continuous and
Synchronous Burst Read has been selected, Valid
Data Ready is high-impedance. It may be tied to
other components with the same Valid Data
Ready signal to create a unique System Ready
signal.
When the system clock frequency is between
33MHz and 50MHz and the Y latency is set to 2,
values of B sampled on odd clock cycles, starting
from the first read are not considered.
Designers should use an external pull-up resistor
of the correct value to meet the external timing re-
quirements for Valid Data Ready rising. Refer to
Figure 20.
Word Organization (WORD). The Word Organi-
zation input, WORD, selects the x16 or x32 Bus
Width on the M58LW128B. The Word Organiza-
tion input is not available on the M58LW128A.
When WORD is Low, VIL, Word-wide x16 Bus
Width is selected; data is read and written to DQ0-
DQ15; DQ16-DQ31 are at high impedance and A1
13/65
M58LW128A, M58LW128Bis the LSB of the address bus. When WORD is
High, VIH, the Double-Word wide x32 Bus Width is
selected and the data is read and written to on
DQ0-DQ31; A2 is the LSB of the address bus and
A1 is don’t care.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the Program/Erase Controller is currently active.
When Ready/Busy is high impedance, the memo-
ry is ready for any read, program or erase opera-
tion. Ready/Busy is Low, VOL, during program and
erase operations. When the device is busy it will
not accept any additional Program or Erase com-
mands except Program/Erase Suspend. When the
Program/Erase Controller is idle, or suspended,
Ready Busy can float High through a pull-up resis-
tor.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Ready/Busy is not Low during a reset unless the
reset was applied when the Program/Erase Con-
troller was active; Ready/Busy can rise before Re-
set/Power-Down rises.
Program/Erase Enable (VPP). The Program/
Erase Enable input, VPP, is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
When Program/Erase Enable is Low, VIL, any pro-
gram or erase operation sent to the Command In-
terface will cause the VPP Status bit (bit3) in the
Status Register to be set. When Program/Erase
Enable is High, VIH, program and erase operations
can be performed on unprotected blocks. Pro-
gram/Erase Enable must be kept High during all
Program, Erase, Block Protect and Block Unpro-
tect operations, otherwise the operation is not
guaranteed to succeed and data may become cor-
rupt.
VDD Supply Voltage. The Supply Voltage, VDD,
is the core power supply. All internal circuits draw
their current from the VDD pin, including the Pro-
gram/Erase Controller.
A 0.1μF capacitor should be connected between
the Supply Voltage, VDD, and the Ground, VSS, to
decouple the current surges from the power sup-
ply. The PCB track widths must be sufficient to
carry the currents required during all operations of
the parts, see Table 16, DC Characteristics, for
maximum current supply requirements.
Input/Output Supply Voltage (VDDQ). The In-
put/Output Supply Voltage, VDDQ, is the input/out-
put buffer power supply. All input and output pins
and voltage references are powered and mea-
sured relative to the Input/Output Supply Voltage
pin, VDDQ.
The Input/Output Supply Voltage, VDDQ, must al-
ways be equal or less than the VDD Supply Volt-
age, including during Power-Up.
A 0.1μF capacitor should be connected between
the Input/Output Supply Voltage, VDDQ, and the
Ground, VSSQ, to decouple the current surges
from the power supply. If VDDQ and VDD are con-
nected together then only one decoupling capaci-
tor is required.
Ground (VSS). Ground, VSS, is the reference for
all core power supply voltages.
Ground (VSSQ). Ground, VSSQ, is the reference
for input/output voltage measurements. It is es-
sential to connect VSS and VSSQ to the same
ground.
M58LW128A, M58LW128B
BUS OPERATIONSThe bus operations that control the memory are
described in this section, see Tables 2 and 3, Bus
Operations, for a summary. The bus operation is
selected through the Burst Configuration Register;
the bits in this register are described at the end of
this section.
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Bus Read and Asyn-
chronous Bus Write, no other bus operation can
be performed until the Burst Control Register has
been configured.
Synchronous Read operations and Latch Con-
trolled Bus Read operations can only be used to
read the memory array. The Electronic Signature,
CFI or Status Register will be read in asynchro-
nous mode regardless of the Burst Control Regis-
ter settings.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus OperationsFor asynchronous bus operations refer to Table 3
together with the text below.
Asynchronous Bus Read. Asynchronous Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Status
Register, CFI and Block Protection Status) in the
Command Interface. A valid bus operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 12, Asynchronous Bus Read AC
Waveforms, and Table 17, Asynchronous Bus
Read AC Characteristics, for details of when the
output becomes valid.
Asynchronous Latch Controlled Bus Read.Asynchronous Latch Controlled Bus Read opera-
tions read from the memory cells. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Address Latch Low, VIL and keeping
Write Enable High, VIH; the address is latched on
the rising edge of Address Latch. Once latched,
the Address Inputs can change. Set Output En-
able Low, VIL, to read the data on the Data Inputs/
Outputs; see Figure 13, Asynchronous Latch Con-
trolled Bus Read AC Waveforms and Table 18,
Asynchronous Latch Controlled Bus Read AC
Characteristics for details on when the output be-
comes valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, VIL, Asynchronous Bus Read
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, VIL
throughout the bus operation.
Asynchronous Page Read. Asynchronous Page
Read operations are used to read from several ad-
dresses within the same memory page. Each
memory page is 8 Words or 4 Double-Words and
has the same A4-A23, only A1, A2 and A3 may
change.
Valid bus operations are the same as Asynchro-
nous Bus Read operations but with different tim-
ings. The first read operation within the page has
identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. See Figure 14, Asynchronous Page
Read AC Waveforms and Table 19, Asynchro-
nous Page Read AC Characteristics for details on
when the outputs become valid.
Asynchronous Bus Write. Asynchronous Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts and setting Latch Enable Low, VIL. The Ad-
dress Inputs are latched by the Command
Interface on the rising edge of Chip Enable or
Write Enable, whichever occurs first. The Data In-
puts/Outputs are latched by the Command Inter-
face on the rising edge of Chip Enable or Write
Enable, whichever occurs first. Output Enable
must remain High, VIH, during the whole Asyn-
chronous Bus Write operation. See Figures 15,
and 17, Asynchronous Write AC Waveforms, and
Tables 20 and 21, Asynchronous Write and Latch
Controlled Write AC Characteristics, for details of
the timing requirements.
Asynchronous Latch Controlled Bus Write.Asynchronous Latch Controlled Bus Write opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data to program. Bus Write op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,
VIL. The Address Inputs are latched by the Com-
mand Interface on the rising edge of Latch Enable,
Chip Enable or Write Enable, whichever occurs
15/65
M58LW128A, M58LW128Bfirst. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip En-
able or Write Enable, whichever occurs first. Out-
put Enable must remain High, VIH, during the
whole Asynchronous Bus Write operation. See
Figures 16 and 18 Asynchronous Latch Controlled
Write AC Waveforms, and Tables 20 and 21,
Asynchronous Write and Latch Controlled Write
AC Characteristics, for details of the timing re-
quirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, IDD1.
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Current, IDD3, for Program or Erase operations un-
til the operation completes.
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
current is reduced to IDD2, and the outputs are
high impedance, independent of Chip Enable,
Output Enable or Write Enable.
Table 2. Asynchronous Bus Operations Note:1. X = Don’t Care VIL or VIH. High = VIH or VHH. M15 = 1, Bits M15 and M3 are in the Burst Configuration Register.
M58LW128A, M58LW128B
Synchronous Bus OperationsFor synchronous bus operations refer to Table 3
together with the text below.
Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external ref-
erence clock. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion.
A valid Synchronous Burst Read operation begins
when the address is set on the Address Inputs,
Write Enable is High, VIH, and Chip Enable and
Latch Enable are Low, VIL, during the active edge
of the Clock. The address is latched on the first ac-
tive clock edge when Latch Enable is low, or on
the rising edge of Latch Enable, whichever occurs
first. The data becomes available for output after
the X-latency specified in the Burst Control Regis-
ter has expired. The output buffers are activated
by setting Output Enable Low, VIL. See Figure 7
for an example of a Synchronous Burst Read op-
eration.
The Burst Address Advance input and the Y-laten-
cy specified in the Burst Control Register deter-
mine whether the internal address counter is
advanced on the active edge of the Clock. When
the internal address counter is advanced the Data
Inputs/Outputs change to output the value for the
next address.
In Continuous Burst mode (Burst Length Bit M2-
M0 is set to ‘111’), one Burst Read operation can
access the entire memory sequentially and wrap
at the last address. The Burst Address Advance,
B, must be kept low, VIL, for the appropriate num-
ber of clock cycles. If Burst Address Advance, B,
is pulled High, VIH, the Burst Read will be sus-
pended.
In Continuous Burst Mode, if the starting address
is not associated with a page (4 Word or 2 Double
Word) boundary the Valid Data Ready, R, output
goes Low, VIL, to indicate that the data will not be
ready in time and additional wait-states are re-
quired. The Valid Data Ready output timing (bit
M8) can be changed in the Burst Configuration
Register.
When using the x32 Bus Width certain X-latencies
are not valid and must not be used; see Table 5,
Burst Configuration Register.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 19, 20
and Table 22.
Synchronous Pipelined Burst Read. Synchro-
nous Burst Read operations can be overlapped to
avoid or reduce the X-latency. Pipelined opera-
tions should only be used with Burst Configuration
Register bit M9 = 0 (Y-latency setting).
A valid Synchronous Pipelined Burst Read opera-
tion occurs during a Synchronous Burst Read op-
eration when the new address is set on the
Address Inputs and a Low pulse is applied to Latch
Enable. The data for the new address becomes
valid after the X-latency specified in the Burst Con-
figuration Register has expired.
For optimum operation the address should be
latched on the correct clock cycle. Table 4 gives
the clock cycle for each valid X- and Y-latency set-
ting. Only these settings are valid, other settings
must not be used. There is always one Y-Latency
period where the data is not valid. If the address is
latched later than the clock cycle specified in Ta-
bles 4 then additional cycles where the data is not
valid are inserted. See Figure 8 for an example of
a Synchronous Pipelined Burst Read operation.
Here the X-latency is 8, the Y-latency is 1 and the
burst length is 4; the first address is latched on cy-
cle 1 while the next address is latched on cycle 6,
as shown in Table 4.
Synchronous Pipelined Burst Read operations
should only be performed on Burst Lengths of 4 or
8 with a x16 Bus Width or a Burst Length of 4 with
a x32 Bus Width.
Suspending a Pipelined Synchronous Burst Read
operation is not recommended.
Synchronous Burst Read Suspend. During a
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is sus-
pended when both Output Enable and Burst Ad-
dress Advance are High, VIH. The Burst Address
Advance going High, VIH, stops the burst counter
and the Output Enable going High, VIH, inhibits the
data outputs. The Synchronous Burst Read oper-
ation can be resumed by setting Output Enable
Low. See Figure 7 for an example of a Synchro-
nous Burst Read Suspend operation.
17/65
M58LW128A, M58LW128B
Table 3. Synchronous Burst Read Bus OperationsNote:1. X = Don’t Care, VIL or VIH. M15 = 0, Bit M15 is in the Burst Configuration Register. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.
Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read
M58LW128A, M58LW128B
Figure 7. Synchronous Burst Read OperationNote: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words or Double Words), M6 = 1 (Valid
Clock Edge = Rising Clock Edge), M7=0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11= 0011 (X-
Latency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.
Figure 8. Example Synchronous Pipelined Burst Read OperationNote: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words or Double Words), M6 = 1 (Valid
Clock Edge = Rising Clock Edge), M7=0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11= 0011 (X-
Latency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.
19/65
M58LW128A, M58LW128B
Figure 9. Example Burst Address Advance and Burst Abort operationsNote:1. In this example the Burst Configuration Register is set with M2-M0 = 010 (Burst Length = 8 Words), M6 = 1 (Valid Clock Edge =
Rising Clock Edge), M7=0 or 1 (Burst Type = Interleaved or Sequential), M9 = 1 (Y-Latency = 2), M14-M11= 0011 (X-Latency =
8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock
cycles, starting from the first read are not considered.
M58LW128A, M58LW128B
Burst Configuration RegisterThe Burst Configuration Register is used to config-
ure the type of bus access that the memory will
perform.
The Burst Configuration Register is set through
the Command Interface and will retain its informa-
tion until it is re-configured, the device is reset, or
the device goes into Reset/Power-Down mode.
The Burst Configuration Register bits are de-
scribed in Table 5. They specify the selection of
the burst length, burst type, burst X and Y laten-
cies and the Read operation.
Read Select Bit (M15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous accesses.
X-Latency Bits (M14-M11). The X-Latency bits
are used during Synchronous Bus Read opera-
tions to set the number of clock cycles between
the address being latched and the first data be-
coming available. For correct operation the X-La-
tency bits can only assume the values in Table 5,
Burst Configuration Register. The X-Latency bits
should also be selected in conjunction with Table
8, Burst Performance to ensure valid settings.
Y-Latency Bit (M9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in M9.
When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every second clock cycle. See Table 5,
Burst Configuration Register and Table 8, Burst
Performance, for valid combinations of the Y-La-
tency, the X-Latency and the Clock frequency.
Valid Data Ready Bit (M8). The Valid Data
Ready bit controls the timing of the Valid Data
Ready output pin, R. When the Valid Data Ready
bit is ’0’ the Valid Data Ready output pin is driven
Low for the active clock edge when invalid data is
output on the bus. When the Valid Data Ready bit
is ’1’ the Valid Data Ready output pin is driven Low
one clock cycle prior to invalid data being output
on the bus.
Burst Type Bit (M7). The Burst Type bit is used
to configure the sequence of addresses read as
sequential or interleaved. When the Burst Type bit
is ’0’ the memory outputs from interleaved ad-
dresses; when the Burst Type bit is ’1’ the memory
outputs from sequential addresses. See Tables 6
and 7, Burst Type Definition, for the sequence of
addresses output from a given starting address in
each mode.
Valid Clock Edge Bit (M6). The Valid Clock Edge
bit, M6, is used to configure the active edge of the
Clock, K, during Synchronous Burst Read opera-
tions. When the Valid Clock Edge bit is ’0’ the fall-
ing edge of the Clock is the active edge; when the
Valid Clock Edge bit is ’1’ the rising edge of the
Clock is active.
Latch Enable Bit (M3). The Latch Enable bit is
used to select between Asynchronous Random
Read and Asynchronous Latch Enable Controlled
Read. When the Latch Enable bit is set to ‘0’ Ran-
dom read is selected; when it is set to ‘1’ Latch En-
able Controlled Read is selected. To enable these
Asynchronous Read configurations M15 must be
set to ‘1’.
Burst Length Bit (M2-M0). The Burst Length bits
set the maximum number of Words or Double-
Words that can be output during a Synchronous
Burst Read operation before the address wraps.
Table 5, Burst Configuration Register gives the
valid combinations of the Burst Length bits that the
memory accepts; Tables 6 and 7, Burst Type Def-
inition, give the sequence of addresses output
from a given starting address for each length.
M10, M5 and M4 are reserved for future use.
21/65
M58LW128A, M58LW128B
Table 5. Burst Configuration Register
M58LW128A, M58LW128B
Table 6. Burst Type Definition (x16 Bus Width)Note: X = 0 or 1.
Table 7. Burst Type Definition (x32 Bus Width)Note: X = 0 or 1.
23/65
M58LW128A, M58LW128B
Table 8. Burst Performance
M58LW128A, M58LW128B
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
9, Commands. Refer to Table 9 in conjunction with
the text descriptions below.
After Power-Up or a Reset operation the memory
enters Read mode.
Synchronous Read operations and Latch Con-
trolled Bus Read operations can only be used to
read the memory array. The Electronic Signature,
CFI or Status Register will be read in Asynchro-
nous mode regardless of the Burst Control Regis-
ter settings. Once the memory returns to Read
Memory Array mode the bus will resume the set-
ting in the Burst Configuration Register automati-
cally.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to Read
mode. One Bus Write cycle is required to issue the
Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program, Erase, Block Protect or Blocks Unpro-
tect operation the memory will not accept the Read
Memory Array command until the operation com-
pletes.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code and the
Block Protection Status. One Bus Write cycle is re-
quired to issue the Read Electronic Signature
command. Once the command is issued subse-
quent Bus Read operations read the Manufacturer
Code, the Device Code or the Block Protection
Status until another command is issued; see Table
10, Read Electronic Signature.
Read Query Command. The Read Query Com-
mand is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash In-
terface Memory Area. See Appendix B, Tables 29,
30, 31, 32, 33 and 34 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
Note that the addresses for the Common Flash In-
terface Memory Area are A1-A23 for the
M58LW128A and A2-A23 for the M58LW128B, re-
gardless of the Bus Width selected.
Read Status Register Command. The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued.
The Status Register information is present on the
output data bus (DQ1-DQ7) when both Chip En-
able and Output Enable are low, VIL.
See the section on the Status Register and Table
12 for details on the definitions of the Status Reg-
ister bits
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect or Block
Unprotect command is issued. If any error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program,
Erase or Resume command.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 11.
See Appendix C, Figure 27, Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Write to Buffer and Program Command. The
Write to Buffer and Program command is used to
program the memory array.
Up to 2 pages of 8 Words (or 4 Double Words) can
be loaded into the Write Buffer and programmed
into the memory. The 2 pages are selected by ad-
dress A4. Each Write Buffer has the same A5 -A23
addresses.
25/65
M58LW128A, M58LW128BFour successive steps are required to issue the
command. One Bus Write operation is required to set up
the Write to Buffer and Program Command. Is-
sue the set up command with the selected
memory Block Address where the program op-
eration should occur (any address in the block
where the values will be programmed can be
used). Any Bus Read operations will start to out-
put the Status Register after the 1st cycle. Use one Bus Write operation to write the same
block address along with the value N on the
Data Inputs/Output, where N+1 is the number of
Words (x16 Bus Width) or Double Words (x32
Bus Width) to be programmed. Use N+1 Bus Write operations to load the ad-
dress and data for each Word or Double Word
into the Write Buffer. See the constraints on the
address combinations listed below. The ad-
dresses must have the same A5-A23. Finally, use one Bus Write operation to issue the
final cycle to confirm the command and start the
Program operation.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper-
ation without affecting the data in the memory ar-
ray. The Status Register should be cleared before
re-issuing the command.
The minimum buffer size for a program operation
is an 8 Word (or 4 Double Word) page. Inside the
page the 8 Words are selected by addresses A3,
A2 and A1.
For any page, only one Write to Buffer and Pro-
gram Command can be issued inside a previously
erased block. Any further Program operations on
that page must be preceded by an Erase operation
on the respective block.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command or by using the
Blocks Temporary Unprotect feature of the Reset/
Power-Down pin, RP.
See Appendix C, Figure 25, Write to Buffer and
Program Flowchart and Pseudo Code, for a sug-
gested flowchart on using the Write to Buffer and
Program command.
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command is used to pause a
Write to Buffer and Program or Erase operation.
The command will only be accepted during a Pro-
gram or an Erase operation. It can be issued at
any time during an Erase operation but will only be
accepted during a Write to Buffer and Program
command if the Program/Erase Controller is run-
ning.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 11.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Write to Buffer and
Program, and the Program Suspend commands
will also be accepted. When a program operation
is completed inside a Block Erase Suspend the
Read Memory Array command must be issued to
reset the device in Read mode, then the Erase Re-
sume command can be issued to complete the
whole sequence. Only the blocks not being erased
may be read or programmed correctly.
See Appendix C, Figure 26, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
28, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
Set Burst Configuration Register Command.The Set Burst Configuration Register command is
used to write a new value to the Burst Configura-
tion Control Register which defines the burst
length, type, X and Y latencies, Synchronous/
M58LW128A, M58LW128BAsynchronous Read mode and the valid Clock
edge configuration.
Two Bus Write cycles are required to issue the Set
Burst Configuration Register command. Once the
command is issued the memory returns to Read
mode as if a Read Memory Array command had
been issued.
The value for the Burst Configuration Register is
always presented on A2-A17, regardless of the
bus width that is selected. M0 is on A2, M1 on A3,
etc.; the other address bits are ignored.
Block Protect Command. The Block Protect
command is used to protect a block and prevent
Program or Erase operations from changing the
data in it. Two Bus Write cycles are required to is-
sue the Block Protect command; the second Bus
Write cycle latches the block address in the inter-
nal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits.
During the Block Protect operation the memory will
only accept the Read Status Register command.
All other commands will be ignored. Typical Block
Protection times are given in Table 11.
The Block Protection bits are non-volatile, once
set they remain set through Reset and Power-
Down/Power-Up. They are cleared by a Blocks
Unprotect command or temporary disabled by
raising the Reset/Power-Down pin to VHH and
holding it at that level throughout a Block Erase or
Write to Buffer and Program command.
Blocks Unprotect Command. The Blocks Un-
protect command is used to unprotect all of the
blocks. Two Bus Write cycles are required to issue
the Blocks Unprotect command; the second Bus
Write cycle starts the Program/Erase Controller.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits.
During the Block Unprotect operation the memory
will only accept the Read Status Register com-
mand. All other commands will be ignored. Typical
Block Protection times are given in Table 11.
27/65
M58LW128A, M58LW128B
Table 9. CommandsNote: X Don’t Care; PA Program Address; PD Program Data; BA Any address in the Block; N+1 Number of Addresses to Program;
BCR Burst Configuration Register value.
Table 10. Read Electronic SignatureNote:1. SBA is the Start Base Address of each block. DQ31-DQ16 are available in the M58LW128B only. x32 Bus Width is available in the M58LW128B only. The address is presented on A22-A2 in x32 mode, and on A22-A1 in x16 mode.
M58LW128A, M58LW128B
Table 11. Program, Erase Times and Program Erase Endurance CyclesNote: (TA = 0 to 70°C; VDD = 2.7V to 3.6V; VDDQ =1.8V)
29/65
M58LW128A, M58LW128B
STATUS REGISTERThe Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re-
sume commands. The Status Register can be
read from any address.
The Status Register can only be read using Asyn-
chronous Bus Read operations. Once the memory
returns to Read Memory Array mode the bus will
resume the setting in the Burst Configuration Reg-
ister automatically.
The contents of the Status Register can be updat-
ed during an Erase or Program operation by tog-
gling the Output Enable pin or by dis-activating
(Chip Enable, VIH) and then reactivating (Chip En-
able and Output Enable, VIL) the device.
During a Program, Block Erase, Block Protect or
Block Unprotect operation only bit 7 is valid, all
other bits are high impedance. Once the operation
is complete bit 7 is High and all other Status regis-
ter bits are valid.
Status Register bits 5, 4, 3 and 1 are associated
with various error conditions and can only be reset
with the Clear Status Register command. The Sta-
tus Register bits are summarized in Table 12, Sta-
tus Register Bits. Refer to Table 12 in conjunction
with the following text descriptions.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low, VOL, the Program/Erase Controller is active
and all other Status Register bits are High Imped-
ance; when the bit is High, VOH, the Program/
Erase Controller is inactive.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control-
ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con-
troller completes the operation and the bit is High.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status and
Block Protection Status bits should be tested for
errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is Low, VOL,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is High, VOH, a
Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
When the Erase Status bit is Low, VOL, the mem-
ory has successfully verified that the block has
erased correctly or all blocks have been unprotect-
ed successfully. When the Erase Status bit is
High, VOH, the erase operation has failed. De-
pending on the cause of the failure other Status
Register bits may also be set to High, VOH. If only the Erase Status bit (bit 5) is set High,
VOH, then the Program/Erase Controller has
applied the maximum number of pulses to the
block and still failed to verify that the block has
erased correctly or that all the blocks have been
unprotected successfully. If the failure is due to an erase or blocks
unprotect with VPP low, VOL, then VPP Status bit
(bit 3) is also set High, VOH. If the failure is due to an erase on a protected
block then Block Protection Status bit (bit 1) is
also set High, VOH. If the failure is due to a program or erase
incorrect command sequence then Program
Status bit (bit 4) is also set High, VOH.
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program or Block Protect fail-
ure. The Program Status bit should be read once
M58LW128A, M58LW128Bthe Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
When the Program Status bit is Low, VOL, the
memory has successfully verified that the Write
Buffer has programmed correctly or the block is
protected. When the Program Status bit is High,
VOH, the program or block protect operation has
failed. Depending on the cause of the failure other
Status Register bits may also be set to High, VOH. If only the Program Status bit (bit 4) is set High,
VOH, then the Program/Erase Controller has
applied the maximum number of pulses to the
byte and still failed to verify that the Write Buffer
has programmed correctly or that the Block is
protected. If the failure is due to a program or block protect
with VPP low, VOL, then VPP Status bit (bit 3) is
also set High, VOH. If the failure is due to a program on a protected
block then Block Protection Status bit (bit 1) is
also set High, VOH. If the failure is due to a program or erase
incorrect command sequence then Erase
Status bit (bit 5) is also set High, VOH.
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify if a Program, Erase, Block Protec-
tion or Block Unprotection operation has been at-
tempted when VPP is Low, VIL. The VPP pin is only
sampled at the beginning of a Program or Erase
operation.
When the VPP Status bit is Low, VOL, no Program,
Erase, Block Protection or Block Unprotection op-
erations have been attempted with VPP Low, VIL,
since the last Clear Status Register command, or
hardware reset. When the VPP Status bit is High,
VOH, a Program, Erase, Block Protection or Block
Unprotection operation has been attempted with
VPP Low, VIL.
Once set High, the VPP Status bit can only be reset
by a Clear Status Register command or a hard-
ware reset. If set High it should be reset before a
new Program, Erase, Block Protection or Block
Unprotection command is issued, otherwise the
new command will appear to fail.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive); after a Program/Erase Suspend
command is issued the memory may still complete
the operation rather than entering the Suspend
mode.
When the Program Suspend Status bit is Low,
VOL, the Program/Erase Controller is active or has
completed its operation; when the bit is High, VOH,
a Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a protected block.
When the Block Protection Status bit is Low, VOL,
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is High, VOH,
a Program (Program Status bit 4 set High) or
Erase (Erase Status bit 5 set High) operation has
been attempted on a protected block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
31/65
M58LW128A, M58LW128B
Table 12. Status Register BitsNote:1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
M58LW128A, M58LW128B
MAXIMUM RATINGStressing the device above the ratings listed in Ta-
ble 13, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 13. Absolute Maximum RatingsNote:1. Cumulative time at a high voltage level of 10V should not exceed 80 hours on RP pin.
33/65
M58LW128A, M58LW128B
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 14,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 14. Operating and AC Measurement Conditions
Figure 10. AC Measurement Input Output
Waveform
Figure 11. AC Measurement Load Circuit
Table 15. Capacitance Note:1. TA = 25°C, f = 1 MHz Sampled only, not 100% tested.
