M5450B7 ,LED DISPLAY DRIVERSFUNCTIONAL DESCRIPTIONBoth the M5450 and the M5451 are specially de- master-slave configurations. T ..
M54512L , 4 UNIT 50MA TRANSISTOR ARRAY
M5451B7 ,LED DISPLAY DRIVERSBlock DiagramVDDOUTPUT OUTPUTBIT 34 BIT 1BRIGTHNESS20 24 18CONTROL100kΩ19 35 OUTPUT BUFFERSLOAD35 L ..
M5451Q ,LED display driver, 35 outputs/15mA sinkFEATURES SUMMARY Figure 1. Packages■ M5450 34 OUTPUTS/15mA SINK ■ M5451 35 OUTPUTS/15mA SINK ■ CURR ..
M5451QT ,LED DISPLAY DRIVERSAbsolute Maximum Ratings" may causes permanent damage to the device. This is a stress ratingonly an ..
M54521P , 5-UNIT 500MA DARLINGTON TRANSISTOR ARRAY
M74LS73AP , DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH RESET
M74LS96P , 5-Bit Shift Register
M74VHC1G125DFT1G , Noninverting 3−State Buffer
M74VHC1G125DTT1G , Noninverting 3−State Buffer
M74VHC1G126DFT1G , Noninverting 3−State Buffer
M74VHC1G126DFT2G , Noninverting 3−State Buffer
M5450B7-M5451B7-M5451Q-M5451QT
LED DISPLAY DRIVERS
1/12April 2004
M5450
M5451LED DISPLAY DRIVERS
REV. 2
FEATURES SUMMARY M5450 34 OUTPUTS/15mA SINK M5451 35 OUTPUTS/15mA SINK CURRENT GENERATOR OUTPUTS (NO
EXTERNAL RESISTORS REQUIRED) CONTINUOUS BRIGHTNESS CONTROL SERIAL DATA INPUT ENABLE (ON M5450) WIDE SUPPLY VOLTAGE OPERATION TTL COMPATIBILITY
Application Examples: MICROPROCESSOR DISPLAYS INDUSTRIAL CONTROL INDICATOR RELAY DRIVER INSTRUMENTATION READOUTS
DESCRIPTIONThe M5450 and M5451 are monolithic MOS inte-
grated circuits produced with an N-channel silicon
gate technology. They are available in 40-pin dual
in-line plastic packages.
A single pin controls the LED display brightness by
setting a reference current through a variable re-
sistor connected to VDD or to a separate supply of
13.2V maximum.
Figure 1. Packages
M5450, M5451
Figure 2. Pin Connection
Figure 3. Block Diagram
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M5450, M5451
Table 1. Absolute Maximum RatingsNote: Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
FUNCTIONAL DESCRIPTIONBoth the M5450 and the M5451 are specially de-
signed to operate 4 or 5-digit alphanumeric dis-
plays with minimal interface with the display and
the data source. Serial data transfer from the data
source to the display driver is accomplished with 2
signals, serial data and clock. Using a format of a
leading "1" followed by the 35 data bits allows data
transfer without an additional load signal. The 35
data bits are latched after the 36th bit is complete,
thus providing non-multiplexed, direct drive to the
display.
Outputs change only if the serial data bits differ
from the previous time.
Display brightness is determined by control of the
output current LED displays.
A 1nF capacitor should be connected to bright-
ness control, pin 19, to prevent possible oscilla-
tions. block diagram is shown in Figure 3. For the
M5450 a DA TA ENABLE is used instead of the
35th output. The DAT A ENABLE input is a metal
option for the M5450.
The output current is typically 20 times greater
than the current into pin 19, which is set by an ex-
ternal variable resistor. There is an internal limiting
resistor of 400W nominal value.
Figure 4 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35
bits of the shift registers into the latches.
At the low state of the clock a RESET signal is
generated which clears all the shift registers for
the next set of data. The shift registers are static
master-slave configurations. There is no clear for
the master portion of the first shift register, thus al-
lowing continuous operation.
There must be a complete set of 36 clocks or the
shift registers will not clear.
When power is first applied to the chip an internal
power ON reset signal is generated which resets
all registers and all latches. The START bit and the
first clock return the chip to its normal operation.
Bit 1 is the first bit following the start bit and it will
appear on Pin 18. A logical "1" at the input will turn
on the appropriate LED.
Figure 5 shows the timing relationship between
Data, Clock and DATA ENABLE.
A max clock frequency of 0.5MHz is assumed. For
applications where a lesser number of outputs are
used, it is possible to either increase the current
per output or operate the part at higher than 1V
VOUT.
The following equation can be used for calcula-
tions.
Tj = [(VOUT) (ILED) (No. of segments) + (VDD ×
7mA)] (124°C/W) + Tamb
where :
Tj = junction temperature (150°C max)
VOUT = the voltage at the LED driver outputs
ILED = the LED current
124°C/W = thermal coefficient of the package
Tamb = ambient temperature
The above equation was used to plot Figure 6, Fig-
ure 7 and Figure 8.
M5450, M5451
Table 2. Static Electrical Characteristics
(Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified)Note:1. Output matching is calculated as the percent variation from I MAX + IMIN/2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. Absolute maximum for each output should be limited to 40mA. The VO voltage should be regulated by the user. See Figure 7 and Figure 8 for allowable VO versus IO operation.
Figure 4. Input Data Format
5/12
M5450, M5451
Figure 5. Figure 6.
Figure 7. Figure 8.
M5450, M5451
TYPICAL APPLICATIONS
Figure 9. Basic Electronically Tuned Radio Or Tv System
Figure 10. Duplexing 8 Digits With One M5450
