M5156 ,A-LAW Companding CodecG " 0
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M5156
A-LAW COMPANDING CODEC
. :5-VOLT POW ..
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M5156
A-LAW Companding Codec
diCifr/tir' SGSra'il'M(0Uil (OR]
's5iffi' memgmemgmee
A-LAW COMPANDING CODEC
:5-VOLT POWER SUPPLIES
LOW POWER DISSIPATION - 30mW (Typ)
FOLLOWS THE A-LAW COMPANDING CODE
INCLUDES CCITT RECOMMENDED EVEN-
ORDER-BIT INVERSION
" SYNCHRONOUS OR ASYNCHRONOUS
OPERATION
'' ON-CHIP SAMPLE AND HOLD
" ON-CHIP OFFSET NULL CIRCUIT ELIMI-
NATES LONG-TERM DRIFT ERRORS AND
NEED FOR TRIMMING
" MINIMAL EXTERNAL CIRCUITRY REQUIRED
" SERIAL DATA OUTPUT OF 64kb/s THROUGH
2.1 Mb/s AT 8kHz SAMPLING RATE
" SEPARATE ANALOG AND DIGITAL
GROUNDS REDUCE NOISE PROBLEMS
DESCRIPTION
The M5156 is a monolithic CMOS companding
CODEC that contains two sections : (1) An analog-
to-digital converter with a transfer characteristic
conforming to the A-law companding code and (2)
a digital-to-analog converter that also conforms to
the A-law code.
PIN CONNECTION (top view)
These two sections form a coder-decoder designed
to meet the needs of the telecommunications indus-
try for per-channel voice-frequency CODECs used
in digital switching and transmission systems. Digi-
tal input and output are in serial format. Actual trans-
mission and reception of 8-bit data words contain-
ing the analog information is done at a 64kb/s
through 2.1Mb/s rate with analog signal sampling
occuring at an 8kHz rate. A sync pulse input is pro-
vided for synchronizing transmission and reception
of multi-channel information being multiplexed over
a single transmission line.
DIP-16
ORDER CODES : M5156Fl (Ceramic)
ANALOG INPUT 1
It + 2
MASTER CLOCK 5
XMIT SYNC 6
XMIT CLOCK 7
DIGITAL OUTPUT a
16 "+vmar
15 --vr,Er
“ANALOG GROUND
" ANALOG OUTPUT
" DIGITAL INPUT
" DIGITAL GROUND
10 RCV CLOCK
9 -RCV SYNC
December 1988
BLOCK DIAGRAM
YRANWIY
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ANALOG
DIGIIAl
III]: BIT
CONVERTER
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Cutctt
RECKWE
S(CYION
MASTER _ S(OUEME
CUXZI CONTROLLER
DIGITAK -
" BIT LATCH
AANALOG
FUNCTIONAL DESCRIPTION
PCM SYSTEM BLOCK DIAGRAM
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+ VREF AND - VREF
Input. Pins 16 and 15. These positive and negative
reference voltages provide the conversion referen-
ces for the digital-to-analog converters in the
M5156. + VREF and - VREF must maintain
100ppM/°C regulation over the operating tempera-
2/11 m scs-mowisom
ture range. Variation of the reference directly affects
system gain.
ANALOG INPUT
Input. Pin 1. Voice-frequency analog signals that are
bandwidth-limited to 4kHz are input at this pin. Typi-
cally, they are then sampled at an 8kHz rate. (See
figure 1). The analog input must remain between +
VREF and - VREF for accurate conversion. The rec-
ommended input interface circuit is shown in figure
MASTER CLOCK
Input. Pin 5. This signal provides the basic timing
and control signals required for all internal conver-
sions. It does not have to be synchronized with RCV
SYNC, RCV CLOCK, XMIT SYNC or XMIT CLOCK
and is not internally related to them.
XMIT SYNC
Input. Pin 6, This input is synchronized with XMIT
CLOCK. When XMIT SYNC goes high, the digital
output is activated and the A/D conversion begins
on the next positive edge of MASTER CLOCK. The
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