M50LPW080N5 ,8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (LPC Interface) . . . . . . 7 ..
M50LPW116N1 ,16 MBIT (2MB X8, BOOT BLOCK) 3V SUPPLY LOW PIN COUNT FLASH MEMORYfeatures an asymmetrical blockarchitecture. It has an array of 50 blocks: 1 BootBlock of 16KBytes, ..
M50LPW116N5G ,16 MBIT (2MB X8, BOOT BLOCK) 3V SUPPLY LOW PIN COUNT FLASH MEMORYLogic Diagram (LPC Interface), and Table 1,memories on a bus. The value on addressesSignal Names (L ..
M51203FP , VOLTAGE COMPARATOR
M51203FP , VOLTAGE COMPARATOR
M51203FP , VOLTAGE COMPARATOR
M65664FP , PICTURE-IN-PICTURE SIGNAL PROCESSING
M65665CSP , PICTURE-IN-PICTURE SIGNAL PROCESSING
M65665FP , PICTURE-IN-PICTURE SIGNAL PROCESSING
M65665FP , PICTURE-IN-PICTURE SIGNAL PROCESSING
M65669SP , PICTURE-IN-PICTURE SIGNAL PROCESSING
M65669SP , PICTURE-IN-PICTURE SIGNAL PROCESSING
M50LPW080N5
8 Mbit 1Mb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
1/44August 2004
M50LPW0808 Mbit (1M x8, Uniform Block)
3V Supply Low Pin Count Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VCC = 3.0 to 3.6V for Program, Erase and
Read Operations
–VPP = 12V for Fast Program and Fast
Erase (optional) TWO INTERFACES Low Pin Count (LPC) Standard Interface
for embedded operation with PC
Chipsets. Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility. LOW PIN COUNT (LPC) HARDWARE
INTERFACE MODE 5 Signal Communication Interface
supporting Read and Write Operations Hardware Write Protect Pins for Block
Protection Register Based Read and Write
Protection 5 Additional General Purpose Inputs for
platform design flexibility Synchronized with 33MHz PCI clock PROGRAMMING TIME 10µs typical Quadruple Byte Programming Option 16 UNIFORM 64 Kbyte MEMORY BLOCKS PROGRAM/ERASE CONTROLLER Embedded Byte Program and Block/Chip
Erase algorithms Status Register Bits PROGRAM and ERASE SUSPEND Read other Blocks during Program/Erase
Suspend Program other Blocks during Erase
Suspend FOR USE in PC BIOS APPLICATIONS ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 2Fh
Figure 1. Packages
M50LPW080
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. Logic Diagram (LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1. Signal Names (LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Memory Identification Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Low Pin Count (LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Input/Output Communications (LAD0-LAD3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Input Communication Frame (LFRAME). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Identification Inputs (ID0-ID1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 4. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .11Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Low Pin Count (LPC) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3/44
M50LPW080Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 5. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 7. LPC Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 6. LPC Bus Read Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 8. LPC Bus Write Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 7. LPC Bus Write Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 9. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS. . . . . . . . . . . . . . . . . . . . . . .21Table 12. Low Pin Count Register Configuration Map (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
M50LPW080
General Purpose Input Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Table 13. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 14. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 15. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 16. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Table 17. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 18. LPC Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 19. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 8. LPC Interface AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 9. A/A Mux Interface AC Testing Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 20. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 21. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 10.LPC Interface Clock Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 22. LPC Interface Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 11.LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 23. LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 12.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 24. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 13.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 25. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 14.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 26. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Figure 15.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . .33
Table 27. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 34
Figure 16.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . .35
Table 28. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. .35
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Figure 17.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 18.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . .38
Figure 19.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . .39
Figure 20.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . .40
Figure 21.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 22.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .42
5/44
M50LPW080
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Table 30. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
M50LPW080
SUMMARY DESCRIPTIONThe M50LPW080 is a 8 Mbit (1Mb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW080 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
and PLCC32 packages and it is supplied with all
the bits erased (set to ’1’).
7/44
M50LPW080
Figure 2. Logic Diagram (LPC Interface)
Figure 3. Logic Diagram (A/A Mux Interface)
Table 1. Signal Names (LPC Interface)
Table 2. Signal Names (A/A Mux Interface)
M50LPW080
9/44
M50LPW080
Figure 5. TSOP Connections
Table 3. Memory Identification Input Configuration
M50LPW080
SIGNAL DESCRIPTIONSThere are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Low Pin Count (LPC) Signal DescriptionsFor the Low Pin Count (LPC) Interface see Figure
2. and Table 1..
Input/Output Communications (LAD0-LAD3).All Input and Output Communication with the
memory take place on these pins. Addresses and
Data for Bus Read and Bus Write operations are
encoded on these pins.
Input Communication Frame (LFRAME). The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Commu-
nication Frame is Low, VIL, on the rising edge of
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, VIH, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID1). The Identification
Inputs (ID0-ID1) allow to address up to 4 memo-
ries on a bus. The value on addresses A20-A21 is
compared to the hardware strapping on the ID0-
ID1 pins to select which memory is being ad-
dressed. For an address bit to be ‘1’ the corre-
spondent ID pin can be left floating or driven Low,
VIL; an internal pull-down resistor is included with
a value of RIL. For an address bit to be ‘0’ the cor-
respondent ID pin must be driven High, VIH; there
will be a leakage current of ILI2 through each pin
when pulled to VIH (see Table 21.).
By convention the boot memory must have ID0-
ID1 pins left floating or driven Low, VIL and a ‘11’
value on A20-A21 and all additional memories
take sequential ID0-ID1 configuration, as shown in
Table 3..
General Purpose Inputs (GPI0-GPI4). The Gener-
al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg-
ister holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register un-
til after the cycle is complete. These pins must not
be left to float, they should be driven Low, VIL, or
High, VIH.
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, VIL; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
current of ILI2 through each pin when pulled to VIH;
see Table 21..
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, VIL, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, VIH, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock in-
put is used to prevent the Top Block (Block 15)
from being changed. When Top Block Lock, TBL,
is set Low, VIL, Program and Block Erase opera-
tions in the Top Block have no effect, regardless of
the state of the Lock Register. When Top Block
Lock, TBL, is set High, VIH, the protection of the
Block is determined by the Lock Register. The
state of Top Block Lock, TBL, does not affect the
protection of the Main Blocks (Blocks 0 to 14).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Block Erase operation is initiated and
must not be changed until the operation completes
or unpredictable results may occur. Care should
be taken to avoid unpredictable behavior by
changing TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP, is
set Low, VIL, Program and Block Erase operations
in the Main Blocks have no effect, regardless of
the state of the Lock Register. When Write Protect,
WP, is set High, VIH, the protection of the Block is
determined by the Lock Register. The state of
11/44
M50LPW080Write Protect, WP, does not affect the protection of
the Top Block (Block 15).
Write Protect, WP, must be set prior to a Program
or Block Erase operation is initiated and must not
be changed until the operation completes or un-
predictable results may occur. Care should be tak-
en to avoid unpredictable behavior by changing
WP during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have assigned functions in this revision of the
part. They must be left disconnected.
Table 4. Block Addresses
Address/Address Multiplexed (A/A Mux)
Signal DescriptionsFor the Address/Address Multiplexed (A/A Mux)
Interface see Figure 3. and Table 2..
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on the rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase Sus-
pend command. When Ready/Busy is High, VOH,
the memory is ready for any Read, Program or
Erase operation.
Supply Signal DescriptionsThe Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid. After VCC
becomes valid the Command Interface is reset to
Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Pro-
gram (see the Quadruple Byte Program Command
description) and Fast Erase options of the memory
and to protect the memory. When VPP < VPPLK
Program and Erase operations cannot be per-
formed and an error is reported in the Status Reg-
ister if an attempt to change the memory contents
is made. When VPP = VCC Program and Erase op-
erations take place as normal. When VPP = VPPH
Fast Program (if a Quadruple Byte Program Com-
mand is performed) and Fast Erase operations are
M50LPW080used. Any other voltage input to VPP will result in
undefined behavior and should not be used.
VPP should not be set to VPPH for more than 80
hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt-
age measurements.
BUS OPERATIONSThe two interfaces have similar bus operations but
the signals and timings are completely different.
The Low Pin Count (LPC) Interface is the usual in-
terface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Ad-
dress Multiplexed (A/A Mux) Interface.
Follow the section Low Pin Count (LPC) Bus Op-
erations below and the section Address/Address
Multiplexed (A/A Mux) Interface Bus Operations
below for a description of the bus operations on
each interface.
Low Pin Count (LPC) Bus OperationsThe Low Pin Count (LPC) Interface consists of
four data signals (LAD0-LAD3), one control line
(LFRAME) and a clock (CLK). In addition protec-
tion against accidental or malicious data corrup-
tion can be achieved using two further signals
(TBL and WP). Finally two reset signals (RP and
INIT) are available to put the memory into a known
state.
The data signals, control signal and clock are de-
signed to be compatible with PCI electrical specifi-
cations. The interface operates with clock speeds
up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Low Pin Count Registers. A valid Bus
Read operation starts when Input Communication
Frame, LFRAME, is Low, VIL, as Clock rises and
the correct Start cycle is on LAD0-LAD3. On the
following clock cycles the Host will send the Cycle
Type + Dir, Address and other control bits on
LAD0-LAD3. The memory responds by outputting
Sync data until the wait-states have elapsed fol-
lowed by Data0-Data3 and Data4-Data7.
See Table 7. and Figure 6. for a description of the
Field definitions for each clock cycle of the trans-
fer. See Table 23. and Figure 11. for details on the
timings of the signals.
Bus Write. Bus Write operations write to the
Command Interface or Low Pin Count Registers. A
valid Bus Write operation starts when Input Com-
munication Frame, LFRAME, is Low, VIL, as Clock
rises and the correct Start cycle is on LAD0-LAD3.
On the following Clock cycles the Host will send
the Cycle Type + Dir, Address, other control bits,
Data0-Data3 and Data4-Data7 on LAD0-LAD3.
The memory outputs Sync data until the wait-
states have elapsed.
See Table 8. and Figure 7. for a description of the
Field definitions for each clock cycle of the trans-
fer. See Table 23. and Figure 11. for details on the
timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when LFRAME is driven Low,
VIL, during the bus operation; the memory will tri-
state the Input/Output Communication pins,
LAD0-LAD3.
Note that, during a Bus Write operation, the Com-
mand Interface starts executing the command as
soon as the data is fully received; a Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command; the bus, however, will be released
immediately.
Standby. When LFRAME is High, VIH, the mem-
ory is put into Standby mode where LAD0-LAD3
are put into a high-impedance state and the Sup-
ply Current is reduced to the Standby level, ICC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, VIL. RP or INIT must be held
Low, VIL, for tPLPH. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset (see Table 13.). If RP or
INIT goes Low, VIL, during a Program or Erase op-
eration, the operation is aborted and the memory
cells affected no longer contain valid data; the
memory can take up to tPLRH to abort a Program
or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
OperationsThe Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional style interface. The sig-
nals consist of a multiplexed address signals (A0-
13/44
M50LPW080A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
equipment for faster factory programming. Only a
subset of the features available to the Low Pin
Count (LPC) Interface are available; these include
all the Commands but exclude the Security fea-
tures and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, VIH, and Output Enable, G, Low, VIL, in order
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see Figure 13. and
Table 25. for details of when the output becomes
valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Ad-
dress Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, VIH and Write En-
able, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See Figure 14. and Table 26. for details
of the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, VIL. RP must be
held Low, VIL for tPLPH. If RP is goes Low, VIL, dur-
ing a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to tPL-
RH to abort a Program or Erase operation.
Table 5. A/A Mux Bus Operations
Table 6. Manufacturer and Device Codes
M50LPW080
15/44
M50LPW080
M50LPW080
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table 10.. The
following text descriptions should be read in con-
junction with Table 10..
Read Memory Array Command. The Read
Memory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The Read
Status Register command is used to read the Sta-
tus Register. One Bus Write cycle is required to is-
sue the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read Elec-
tronic Signature command. Once the command is
issued subsequent Bus Read operations read the
Manufacturer Code or the Device Code until an-
other command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be read using Bus Read operations using the
addresses in Table 9..
Table 9. Read Electronic Signature
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write opera-
tions are required to issue the command; the sec-
ond Bus Write cycle latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the address falls in a protected block then the
Program operation will abort, the data in the mem-
ory array will not be changed and the Status Reg-
ister will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 15..
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. One of the
Erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 17. for a suggested flowchart on using
the Program command.
Quadruple Byte Program Command. The Qua-
druple Byte Program Command can be only used
in A/A Mux mode to program four adjacent bytes
in the memory array at a time. The four bytes must
differ only for the addresses A0 and A10. Pro-
gramming should not be attempted when VPP is
not at VPPH. The operation can also be executed if
VPP is below VPPH, but result could be uncertain.
Five Bus Write operations are required to issue the
command. The second, the third and the fourth
Bus Write cycle latches respectively the address
and data of the first, the second and the third byte
in the internal state machine. The fifth Bus Write
cycle latches the address and data of the fourth
byte in the internal state machine and starts the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
During the Quadruple Byte Program operation the
memory will only accept the Read Status register
command and the Program/Erase Suspend com-
mand. All other commands will be ignored. Typical
Quadruple Byte Program times are given in Table
15..
Note that the Quadruple Byte Program command
cannot change a bit set to ‘0’ back to ‘1’ and at-
tempting to do so will not cause any modification
on its value. One of the Erase commands must be
used to set all of the bits in the block to ‘1’.
See Figure 18. for a suggested flowchart on using
the Quadruple Byte Program command.
17/44
M50LPW080
Chip Erase Command. The Chip Erase Com-
mand can be only used in A/A Mux mode to erase
the entire chip at a time. Erasing should not be at-
tempted when VPP is not at VPPH. The operation
can also be executed if VPP is below VPPH, but re-
sult could be uncertain. Two Bus Write operations
are required to issue the command and start the
Program/Erase Controller. Once the command is
issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits. During the Chip Erase operation the
memory will only accept the Read Status Register
command. All other commands will be ignored.
Typical Chip Erase times are given in Table 15..
The Chip Erase command sets all of the bits in the
memory to ‘1’. See Figure 20. for a suggested
flowchart on using the Chip Erase command.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the block is protected then the Block Erase oper-
ation will abort, the data in the block will not be
changed and the Status Register will output the er-
ror.
During the Block Erase operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Block
Erase times are given in Table 15..
The Block Erase command sets all of the bits in
the block to ‘1’. All previous data in the block is
lost.
See Figure 21. for a suggested flowchart on using
the Block Erase command.
Clear Status Register Command. The Clear
Status Register command can be used to reset
bits 1, 3, 4 and 5 in the Status Register to ‘0’. One
Bus Write is required to issue the Clear Status
Register command. Once the command is issued
the memory returns to its previous mode, subse-
quent Bus Read operations continue to output the
same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command can be used to
pause a Program or Block Erase operation. One
Bus Write cycle is required to issue the Program/
Erase Suspend command and pause the Pro-
gram/Erase Controller. Once the command is is-
sued it is necessary to poll the Program/Erase
Controller Status bit to find out when the Program/
Erase Controller has paused; no other commands
will be accepted until the Program/Erase Control-
ler has paused. After the Program/Erase Control-
ler has paused, the memory will continue to output
the Status Register until another command is is-
sued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once Program/Erase Control-
ler Status bit indicates that the Program/Erase
Controller is no longer active, the Program Sus-
pend Status bit or the Erase Suspend Status bit
can be used to determine if the operation has com-
pleted or is suspended. For timing on the delay be-
tween issuing the Program/Erase Suspend
command and the Program/Erase Controller
pausing see Table 15..
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume com-
mands will be accepted by the Command Inter-
face. Additionally, if the suspended operation was
Block Erase then the Program command will also
be accepted; only the blocks not being erased may
be read or programmed correctly.
See Figure 19. and Figure 22. for suggested flow-
charts on using the Program/Erase Suspend com-
mand.
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the Program/Erase
Resume command. Once the command is issued
subsequent Bus Read operations read the Status
Register.
M50LPW080
Table 10. CommandsNote: X Don’t Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Addresses, BA Any address in the Block.
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-mand is issued.
Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-sued.
Quadruple Byte Program. This command is only valid in A/A Mux mode. Addresses A1, A2, A3 and A4 must be consecutive addressesdiffering only for address bit A0 and A10. After this command read the Status Register until the command completes and another com-
mand is issued.
Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completesand another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read StatusRegister, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read theStatus Register until the Program/Erase Controller Do not use Invalid or Reserved commands not use Invalid or Reserved commands.
19/44
M50LPW080
STATUS REGISTERThe Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey differ-
ent information and errors on the operation.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any ad-
dress.
The Status Register bits are summarized in Table
11.. The following text descriptions should be read
in conjunction with Table 11..
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that a Block Erase oper-
ation has been suspended and is waiting to be
resumed. The Erase Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Pro-
gram/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block(s)
and still failed to verify that the block(s) has erased
correctly. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block(s) has erased
correctly; when the Erase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the block(s) and still failed to
verify that the block(s) has erased correctly.
Once the Erase Status bit is set to ‘1’ it can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has pro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro-
grammed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that the byte has programmed cor-
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was sampled at a valid voltage; when the
VPP Status bit is ‘1’ the VPP pin has a voltage that
is below the VPP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase opera-
tion cannot be performed.
Once the VPP Status bit set to ‘1’ it can only be re-
set to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
M50LPW080
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Block Erase operation has tried to modify
the contents of a protected block. When the Block
Protection Status bit is to ‘0’ no Program or Block
Erase operations have been attempted to protect-
ed blocks since the last Clear Status Register
command or hardware reset; when the Block Pro-
tection Status bit is ‘1’ a Program or Block Erase
operation has been attempted on a protected
block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Block
Erase command is issued, otherwise the new
command will appear to fail.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
Table 11. Status Register BitsNote:1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
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M50LPW080
LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERSWhen the Low Pin Count Interface is selected sev-
eral additional registers can be accessed. These
registers control the protection status of the Blocks
and read the General Purpose Input pins. See Ta-
ble 12. for an example of the Register Configura-
tion map, valid for the boot memory, i.e. ID0-ID1
floating or driven LOW, VIL and A20-A21 set to ‘1’.
Table 12. Low Pin Count Register Configuration Map (1)Note:1. This map is referred to the boot memory (ID0-ID1 floating or driven, LOW, VIL and A20-A21 set to ‘1’).
Lock RegistersThe Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bit is set, ‘1’, further modifications
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 13. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Block Erase Command).
When the Write Lock Bit is set, ‘1’, the block is
write protected; any operations that attempt to
change the data in the block will fail and the Status
Register will report the error. When the Write Lock
Bit is reset, ‘0’, the block is not write protected
through the Lock Register and may be modified
unless write protected through some other means.
When VPP is less than VPPLK all blocks are pro-
tected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, VIL, then the Top Block (Block 15) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, VIL, then the Main
Blocks (Blocks 0 to 14) are write protected and
cannot be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
M50LPW080
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
General Purpose Input RegisterThe General Purpose Input Register holds the
state of the General Purpose Input pins, GPI0-
GPI4. When this register is read, the state of these
pins is returned. This register is read-only and writ-
ing to it has no effect.
The signals on the General Purpose Input pins
should remain constant throughout the whole Bus
Read cycle in order to guarantee that the correct
data is read.
Table 13. Lock Register Bit DefinitionsNote: Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-15] Lock Reg-
ister (T_MINUS15_LK).
Table 14. General Purpose Input Register DefinitionNote: Applies to the General Purpose Input Register (GPI_REG).
