M50FW040 ,4 MBIT (512KB X8, UNIFORM BLOCK) 3V SUPPLY FIRMWARE HUB FLASH MEMORYLogic Diagram, and Table 1, Signal Names.NC Not Connected InternallyFigure 4. TSOP ConnectionsNC NC ..
M50FW040K ,4 Mbit 512Kb x8, Uniform Block 3V Supply Firmware Hub Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 2. Signal Names (A/A Mux Interface) . . 7Figu ..
M50FW040K1 ,4 MBIT (512KB X8, UNIFORM BLOCK) 3V SUPPLY FIRMWARE HUB FLASH MEMORYM50FW0404 Mbit (512Kb x8, Uniform Block)3V Supply Firmware Hub Flash Memory
M50FW040-K1 ,4 MBIT (512KB X8, UNIFORM BLOCK) 3V SUPPLY FIRMWARE HUB FLASH MEMORYLogic Diagram (FWH Interface) . . . . . 6Table 1. Signal Names (FWH Interface) . . . . . 6 ..
M50FW040K1T ,4 Mbit 512Kb x8, Uniform Block 3V Supply Firmware Hub Flash MemoryFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 3V to 3.6V for Program, Erase and CCRead Op ..
M50FW040K5G ,4 Mbit (512Kb x8, Uniform Block) 3V Supply Firmware Hub Flash MemoryLogic Diagram (FWH Interface) . . . . . 6Table 1. Signal Names (FWH Interface) . . . . . 6 ..
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M64893GP , SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
M64893GP , SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
M64894FP , SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
M64895BGP , I2C BUS FREQUENCY SYNTHESIZER FOR TV/VTR
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M50FW040
4 MBIT (512KB X8, UNIFORM BLOCK) 3V SUPPLY FIRMWARE HUB FLASH MEMORY
1/32March 2002
M50FW0404 Mbit (512Kb x8, Uniform Block)
3V Supply Firmware Hub Flash Memory SUPPLY VOLTAGE
–VCC = 3V to 3.6V for Program, Erase and
Read Operations
–VPP = 12V for Fast Erase (optional) TWO INTERFACES Firmware Hub (FWH) Interface for embedded
operation with PC Chipsets. Address/Address Multiplexed (A/A Mux) In-
terface for programming equipment compati-
bility. FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE 5 Signal Communication Interface supporting
Read and Write Operations Hardware Write Protect Pins for Block Pro-
tection Register Based Read and Write Protection 5 Additional General Purpose Inputs for plat-
form design flexibility Synchronized with 33MHz PCI clock PROGRAMMING TIME: 10μs typical 8 UNIFORM 64 Kbyte MEMORY BLOCKS PROGRAM/ERASE CONTROLLER Embedded Byte Program and Block Erase al-
gorithms Status Register Bits PROGRAM and ERASE SUSPEND Read other Blocks during Program/Erase
Suspend Program other Blocks during Erase Suspend FOR USE in PC BIOS APPLICATIONS ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 2Ch
Figure 1. Logic Diagram (FWH Interface)
M50FW040
Figure 2. Logic Diagram (A/A Mux Interface)
DESCRIPTIONThe M50FW040 is a 4 Mbit (512Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast erasing in production lines an optional 12V
power supply can be used to reduce the erasing
time.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
Figure 3. PLCC ConnectionsNote: Pins 27 and 28 are not internally connected.
3/32
M50FW040
Figure 4. TSOP ConnectionsM50FW040 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
and PLCC32 packages and it is supplied with all
the bits erased (set to ’1’).
SIGNAL DESCRIPTIONSThere are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Firmware Hub (FWH) Signal DescriptionsFor the Firmware Hub (FWH) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Table 1. Signal Names (FWH Interface)
M50FW040
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, VIL; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
current of ILI2 through each pin when pulled to VIH;
see Table 19.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, VIL, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, VIH, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock in-
put is used to prevent the Top Block (Block 7) from
being changed. When Top Block Lock, TBL, is set
Low, VIL, Program and Erase operations in the
Top Block have no effect, regardless of the state
of the Lock Register. When Top Block Lock, TBL,
is set High, VIH, the protection of the Block is de-
termined by the Lock Register. The state of Top
Block Lock, TBL, does not affect the protection of
the Main Blocks (Blocks 0 to 6).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Erase operation is initiated and must not
be changed until the operation completes or un-
predictable results may occur. Care should be tak-
en to avoid unpredictable behavior by changing
TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 6)
from being changed. When Write Protect, WP, is
set Low, VIL, Program and Erase operations in the
Main Blocks have no effect, regardless of the state
of the Lock Register. When Write Protect, WP, is
set High, VIH, the protection of the Block deter-
mined by the Lock Register. The state of Write
Table 2. Signal Names (A/A Mux Interface)
Input/Output Communications (FWH0-FWH3). All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (FWH4). The In-
put Communication Frame (FWH4) signals the
start of a bus operation. When Input Communica-
tion Frame is Low, VIL, on the rising edge of the
Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, VIH, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The Identifica-
tion Inputs select the address that the memory re-
sponds to. Up to 16 memories can be addressed
on a bus. For an address bit to be ‘0’ the pin can
be left floating or driven Low, VIL; an internal pull-
down resistor is included with a value of RIL. For
an address bit to be ‘1’ the pin must be driven
High, VIH; there will be a leakage current of ILI2
through each pin when pulled to VIH; see Table 19.
By convention the boot memory must have ad-
dress ‘0000’ and all additional memories take se-
quential addresses starting from ‘0001’.
General Purpose Inputs (FGPI0-FGPI4). The Gen-
eral Purpose Inputs can be used as digital inputs
for the CPU to read. The General Purpose Inputs
Register holds the values on these pins. The pins
must have stable data from before the start of the
cycle that reads the General Purpose Input Regis-
ter until after the cycle is complete. These pins
must not be left to float, they should be driven Low,
VIL, or High, VIH.
5/32
M50FW040Protect, WP, does not affect the protection of the
Top Block (Block 7).
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated and must not be
changed until the operation completes or unpre-
dictable results may occur. Care should be taken
to avoid unpredictable behavior by changing WP
during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have assigned functions in this revision of the
part. They must be left disconnected.
Address/Address Multiplexed (A/A Mux)
Signal DescriptionsFor the Address/Address Multiplexed (A/A Mux)
Interface see Figure 2, Logic Diagram, and Table
2, Signal Names.
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A18). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A18). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on the rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase Sus-
pend command. When Ready/Busy is High, VOH,
the memory is ready for any Read, Program or
Erase operation.
Supply Signal DescriptionsThe Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid. After VCC
becomes valid the Command Interface is reset to
Read mode.
A 0.1μF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Erase
Table 3. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Minimum Voltage may undershoot to –2V and for less than 20ns during transitions. Maximum Voltage may overshoot to VCC +2V
and for less than 20ns during transitions.
M50FW040option of the memory and to protect the memory.
When VPP < VPPLK Program and Erase operations
cannot be performed and an error is reported in
the Status Register if an attempt to change the
memory contents is made. When VPP = VCC Pro-
gram and Erase operations take place as normal.
When VPP = VPPH Fast Erase operations are
used. Any other voltage input to VPP will result in
undefined behavior and should not be used.
VPP should not be set to VPPH for more than 80
hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt-
age measurements.
BUS OPERATIONSThe two interfaces have similar bus operations but
the signals and timings are completely different.
The Firmware Hub (FWH) Interface is the usual in-
terface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Ad-
dress Multiplexed (A/A Mux) Interface.
Follow the section Firmware Hub (FWH) Bus Op-
erations below and the section Address/Address
Multiplexed (A/A Mux) Interface Bus Operations
below for a description of the bus operations on
each interface.
Firmware Hub (FWH) Bus OperationsThe Firmware Hub (FWH) Interface consists of
four data signals (FWH0-FWH3), one control line
(FWH4) and a clock (CLK). In addition protection
against accidental or malicious data corruption
can be achieved using two further signals (TBL
and WP). Finally two reset signals (RP and INIT)
are available to put the memory into a known
state.
The data signals, control signal and clock are de-
signed to be compatible with PCI electrical specifi-
cations. The interface operates with clock speeds
up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Firmware Hub Registers. A valid Bus
Read operation starts when Input Communication
Frame, FWH4, is Low, VIL, as Clock rises and the
correct Start cycle is on FWH0-FWH3. On the fol-
lowing clock cycles the Host will send the Memory
ID Select, Address and other control bits on
FWH0-FWH3. The memory responds by output-
ting Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
Refer to Table 5, FWH Bus Read Field Definitions,
and Figure 5, FWH Bus Read Waveforms, for a
description of the Field definitions for each clock
cycle of the transfer. See Table 21, FWH Interface
AC Signal Timing Characteristics and Figure 10,
FWH Interface AC Signal Timing Waveforms, for
details on the timings of the signals.
Bus Write. Bus Write operations write to the
Command Interface or Firmware Hub Registers. A
valid Bus Write operation starts when Input Com-
munication Frame, FWH4, is Low, VIL, as Clock
rises and the correct Start cycle is on FWH0-
FWH3. On the following Clock cycles the Host will
send the Memory ID Select, Address, other control
bits, Data0-Data3 and Data4-Data7 on FWH0-
FWH3. The memory outputs Sync data until the
wait-states have elapsed.
Refer to Table 6, FWH Bus Write Field Definitions,
and Figure 6, FWH Bus Write Waveforms, for a
description of the Field definitions for each clock
cycle of the transfer. See Table 21, FWH Interface
AC Signal Timing Characteristics and Figure 10,
FWH Interface AC Signal Timing Waveforms, for
details on the timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when FWH4 is driven Low, VIL,
during the bus operation; the memory will tri-state
the Input/Output Communication pins, FWH0-
FWH3.
Note that, during a Bus Write operation, the Com-
mand Interface starts executing the command as
soon as the data is fully received; a Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command; the bus, however, will be released
immediately.
Standby. When FWH4 is High, VIH, the memory
is put into Standby mode where FWH0-FWH3 are
Table 4. Block Addresses
7/32
M50FW040
Table 5. FWH Bus Read Field Definitions
Figure 5. FWH Bus Read Waveforms
M50FW040
Table 6. FWH Bus Write Field Definitionsput into a high-impedance state and the Supply
Current is reduced to the Standby level, ICC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, VIL. RP or INIT must be held
Low, VIL, for tPLPH. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 14. If RP or
INIT goes Low, VIL, during a Program or Erase op-
eration, the operation is aborted and the memory
cells affected no longer contain valid data; the
memory can take up to tPLRH to abort a Program
or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Figure 6. FWH Bus Write Waveforms
9/32
M50FW040
Address/Address Multiplexed (A/A Mux) Bus
OperationsThe Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional style interface. The sig-
nals consist of a multiplexed address signals (A0-
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
equipment for faster factory programming. Only a
subset of the features available to the Firmware
Hub (FWH) Interface are available; these include
all the Commands but exclude the Security fea-
tures and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, VIH, and Output Enable, G, Low, VIL, in order
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see Figure 12, A/A
Mux Interface Read AC Waveforms, and Table 23,
A/A Mux Interface Read AC Characteristics, for
details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Ad-
dress Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, VIH and Write En-
able, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See Figure 13, A/A Mux Interface Write
AC Waveforms, and Table 24, A/A Mux Interface
Write AC Characteristics, for details of the timing
requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, VIL. RP must be
held Low, VIL for tPLPH. If RP is goes Low, VIL, dur-
ing a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to tPL-
RH to abort a Program or Erase operation.
Table 7. A/A Mux Bus Operations
Table 8. Manufacturer and Device Codes
M50FW040
COMMAND INTERFACEAll Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table 10,
Commands. Refer to Table 10 in conjunction with
the text descriptions below.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read Elec-
tronic Signature command. Once the command is
issued subsequent Bus Read operations read the
Manufacturer Code or the Device Code until an-
other command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be read using Bus Read operations using the
addresses in Table 9.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write opera-
tions are required to issue the command; the sec-
ond Bus Write cycle latches the address and data
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the address falls in a protected block then the
Program operation will abort, the data in the mem-
ory array will not be changed and the Status Reg-
ister will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 11.
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. The Erase
command must be used to set all of the bits in the
block to ‘1’.
See Figure 14, Program Flowchart and Pseudo
Code, for a suggested flowchart on using the Pro-
gram command.
Erase Command. The Erase command can be
used to erase a block. Two Bus Write operations
are required to issue the command; the second
Bus Write cycle latches the block address in the in-
ternal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits.
If the block is protected then the Erase operation
will abort, the data in the block will not be changed
and the Status Register will output the error.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 11.
The Erase command sets all of the bits in the block
to ‘1’. All previous data in the block is lost.
See Figure 16, Erase Flowchart and Pseudo
Code, for a suggested flowchart on using the
Erase command.
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. Once the command is issued the mem-
ory returns to its previous mode, subsequent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program
Table 9. Read Electronic Signature
11/32
M50FW040
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command can be used to
pause a Program or Erase operation. One Bus
Write cycle is required to issue the Program/Erase
Suspend command and pause the Program/Erase
Controller. Once the command is issued it is nec-
essary to poll the Program/Erase Controller Status
bit to find out when the Program/Erase Controller
has paused; no other commands will be accepted
until the Program/Erase Controller has paused.
After the Program/Erase Controller has paused,
the memory will continue to output the Status Reg-
ister until another command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once Program/Erase Control-
ler Status bit indicates that the Program/Erase
Controller is no longer active, the Program Sus-
pend Status bit or the Erase Suspend Status bit
can be used to determine if the operation has com-
pleted or is suspended. For timing on the delay be-
tween issuing the Program/Erase Suspend
command and the Program/Erase Controller
pausing see Table 11.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume com-
mands will be accepted by the Command Inter-
face. Additionally, if the suspended operation was
Erase then the Program command will also be ac-
cepted; only the blocks not being erased may be
read or programmed correctly.
See Figures 15, Program Suspend & Resume
Flowchart and Pseudo Code, and 17, Erase Sus-
pend & Resume Flowchart and Pseudo Code, for
suggested flowcharts on using the Program/Erase
Suspend command.
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
Table 10. CommandsNote: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-mand is issued.
Erase, Program. After these commands read the Status Register until the command completes and another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read StatusRegister, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read theStatus Register until the Program/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved commands.
M50FW040
STATUS REGISTERThe Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey differ-
ent information and errors on the operation.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any ad-
dress.
The Status Register bits are summarized in Table
12, Status Register Bits. Refer to Table 12 in con-
junction with the text descriptions below.
Program/Erase Controller Status (Bit 7). The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is ‘1’ (Program/Erase Controller
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Pro-
gram/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block and
still failed to verify that the block has erased cor-
rectly. The Erase Status bit should be read once
the Program/Erase Controller Status bit is ‘1’ (Pro-
gram/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block has erased cor-
rectly; when the Erase Status bit is ‘1’ the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the block and still failed to ver-
ify that the block has erased correctly.
Once the Erase Status bit is set to ‘1’ the it can
only be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has pro-
grammed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has pro-
grammed correctly; when the Program Status bit is
Table 11. Program and Erase Times(TA = 0 to 70°C or –20 to 85°C; VCC = 3.0 to 3.6V)
Note:1. TA = 25°C, VCC = 3.3V Sampled only, not 100% tested.
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M50FW040
Table 12. Status Register BitsNote:1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that the byte has programmed cor-
rectly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register com-
mand or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was sampled at a valid voltage; when the
VPP Status bit is ‘1’ the VPP pin has a voltage that
is below the VPP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase opera-
tion cannot be performed.
Once the VPP Status bit set to ‘1’ it can only be re-
set to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is is-
sued, otherwise the new command will appear to
fail.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Control-
ler inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has complet-
ed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if the Pro-
gram or Erase operation has tried to modify the
contents of a protected block. When the Block Pro-
tection Status bit is to ‘0’ no Program or Erase op-
erations have been attempted to protected blocks
since the last Clear Status Register command or
hardware reset; when the Block Protection Status
bit is ‘1’ a Program or Erase operation has been at-
tempted on a protected block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to fail.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
M50FW040
Table 13. Firmware Hub Register Configuration MapLock Register and may be modified unless write
protected through some other means.
When VPP is less than VPPLK all blocks are pro-
tected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, VIL, then the Top Block (Block 7) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, VIL, then the Main
Blocks (Blocks 0 to 6) are write protected and can-
not be modified.
After power-up or reset the Write Lock Bit is al-
ways set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data pro-
grammed into the block as expected.
After power-up or reset the Read Lock Bit is al-
ways reset to ‘0’ (not read protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
FIRMWARE HUB (FWH) INTERFACE
CONFIGURATION REGISTERSWhen the Firmware Hub Interface is selected sev-
eral additional registers can be accessed. These
registers control the protection status of the
Blocks, read the General Purpose Input pins and
identify the memory using the Electronic Signature
codes. See Table 13 for the memory map of the
Configuration Registers.
Lock RegistersThe Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bit is set, ‘1’, further modifications
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 14 for details on the bit definitions of the
Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Erase Command). When
the Write Lock Bit is set, ‘1’, the block is write pro-
tected; any operations that attempt to change the
data in the block will fail and the Status Register
will report the error. When the Write Lock Bit is re-
set, ‘0’, the block is not write protected through the
15/32
M50FW040
Firmware Hub (FWH) General Purpose Input
RegisterThe Firmware Hub (FWH) General Purpose Input
Register holds the state of the Firmware Hub Inter-
face General Purpose Input pins, FGPI0-FGPI4.
When this register is read, the state of these pins
is returned. This register is read-only and writing to
it has no effect.
The signals on the Firmware Hub Interface Gener-
al Purpose Input pins should remain constant
throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Manufacturer Code RegisterReading the Manufacturer Code Register returns
the manufacturer code for the memory. The man-
ufacturer code for STMicroelectronics is 20h. This
register is read-only and writing to it has no effect.
Device Code RegisterReading the Device Code Register returns the de-
vice code for the memory, 2Ch. This register is
read-only and writing to it has no effect.
Table 14. Lock Register Bit Definitions(1)Note:1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-7] Lock Reg-
ister (T_MINUS07_LK).
Table 15. General Purpose Inputs Register Definition(1)Note:1. Applies to the General Purpose Inputs Register (FGPI-REG).
M50FW040
Table 16. FWH Interface AC Measurement Conditions
Figure 7. FWH Interface AC Testing Input Output Waveforms
