M50FLW080AN5TG ,8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash MemoryLogic Diagram (FWH/LPC Interface) . 7Figure 3.
M50FLW080ANB5 ,8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash MemoryFEATURES SUMMARY■ FLASH MEMORY Figure 1. Packages– Compatible with either the LPC interface or the ..
M50FLW080ANB5G ,8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memoryapplications– 5 Signal Communication Interface supporting Read and Write Operations– 5 Additional G ..
M50FLW080ANB5G ,8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (FWH/LPC Interface) . 7Table ..
M50FW002K1 ,2 MBIT (256KB X8, BOOT BLOCK) 3V SUPPLY FIRMWARE HUB FLASH MEMORYfeatures an asymmetrical blocked ar-tile memory that can be read, erased and repro- chitecture. The ..
M50FW016N5 , 16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M64886FP , RF Transceiver for Short-range Wireless
M64893GP , SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
M64893GP , SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
M64894FP , SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
M64895BGP , I2C BUS FREQUENCY SYNTHESIZER FOR TV/VTR
M64895BGP , I2C BUS FREQUENCY SYNTHESIZER FOR TV/VTR
M50FLW080AK5-M50FLW080AK5G-M50FLW080AN5-M50FLW080AN5TG-M50FLW080ANB5
8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory
1/53June 2005
M50FLW080A
M50FLW080B8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)
3V Supply Firmware Hub / Low Pin Count Flash Memory
FEATURES SUMMARY FLASH MEMORY Compatible with either the LPC interface
or the FWH interface (Intel Spec rev1.1)
used in PC BIOS applications 5 Signal Communication Interface
supporting Read and Write Operations 5 Additional General Purpose Inputs for
platform design flexibility Synchronized with 33MHz PCI clock 16 BLOCKS OF 64 KBYTES 13 blocks of 64 KBytes each 3 blocks, subdivided into 16 uniform
sectors of 4 KBytes each
Two blocks at the top and one at the
bottom (M50FLW080A)
One block at the top and two at the bottom
(M50FLW080B) ENHANCED SECURITY Hardware Write Protect Pins for Block
Protection Register-based Read and Write
Protection Individual Lock Register for Each 4 KByte
Sector SUPPLY VOLTAGE
–VCC = 3.0 to 3.6V for Program, Erase and
Read Operations
–VPP = 12V for Fast Program and Erase TWO INTERFACES Auto Detection of Firmware Hub (FWH) or
Low Pin Count (LPC) Memory Cycles for
Embedded Operation with PC Chipsets Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility. PROGRAMMING TIME: 10µs typical PROGRAM/ERASE CONTROLLER Embedded Program and Erase algorithms Status Register Bits
M50FLW080A, M50FLW080B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 2. Logic Diagram (FWH/LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1. Signal Names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Addresses (M50FLW080A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Addresses (M50FLW080B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . .10Input/Output Communications (FWH0/LAD0-FWH3/LAD3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Input Communication Frame (FWH4/LFRAME). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .11Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5. Memory Identification Input Configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . .12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . .12Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3/53
M50FLW080A, M50FLW080BBus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 7. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 8. LPC Bus Read Field Definitions (1-Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 9. LPC Bus Read Waveforms (1-Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 9. LPC Bus Write Field Definitions (1 Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 10.LPC Bus Write Waveforms (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 10. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 11. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 12. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Quadruple Byte Program Command (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Double/Quadruple Byte Program Command (FWH Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 13. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Program/Erase Controller Status (Bit SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Erase Suspend Status (Bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Erase Status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Program Status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
VPP Status (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Program Suspend Status (Bit SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Block/Sector Protection Status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 14. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
M50FLW080A, M50FLW080B
FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . .24
Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 15. Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 16. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 17. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . .25
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 18. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 19. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 20. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 21. FWH/LPC Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 22. A/A Mux Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 11.FWH/LPC Interface AC Measurement I/O Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 12.A/A Mux Interface AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 23. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 24. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 14.FWH/LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 25. FWH/LPC Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 15.FWH/LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 26. FWH/LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 16.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 27. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 17.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 28. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 18.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 29. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Figure 19.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . .36
Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 37
Figure 20.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . .38
Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . .38
Figure 21.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . .39
Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data .39
5/53
M50FLW080A, M50FLW080B
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Table 34. M50FLW080A Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . .41
Table 35. M50FLW080B Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . .43
APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . .46
Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . .47
Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . .48
Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . .49
Figure 27.Sector/Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .51
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
M50FLW080A, M50FLW080B
SUMMARY DESCRIPTIONThe M50FLW080 is a 8 Mbit (1M x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing on production
lines, an optional 12V power supply can be used
to reduce the erasing and programming time.
The memory is divided into 16 Uniform Blocks of
64 KBytes each, three of which are divided into 16
uniform sectors of 4 KBytes each (see APPENDIX
A. for details). All blocks and sectors can be
erased independently. So, it is possible to pre-
serve valid data while old data is erased. Blocks
can be protected individually to prevent accidental
program or erase commands from modifying their
contents.
Program and erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified. The command set
to control the memory is consistent with the JE-
DEC standards.
Two different bus interfaces are supported by the
memory: The primary interface, the FWH/LPC
Interface, uses Intel’s proprietary Firmware
Hub (FWH) and Low Pin Count (LPC)
protocol. This has been designed to remove
the need for the ISA bus in current PC
Chipsets. The M50FLW080 acts as the PC
BIOS on the Low Pin Count bus for these PC
Chipsets. The secondary interface, the Address/
Address Multiplexed (or A/A Mux) Interface, is
designed to be compatible with current Flash
Programmers, for production line
programming prior to fitting the device in a PC
Motherboard.
The memory is supplied with all the bits erased
(set to ’1’).
7/53
M50FLW080A, M50FLW080B
Table 1. Signal Names (FWH/LPC Interface)
Table 2. Signal Names (A/A Mux Interface)
M50FLW080A, M50FLW080B
9/53
M50FLW080A, M50FLW080B
Table 3. Addresses (M50FLW080A) Table 4. Addresses (M50FLW080B)Note: Also see APPENDIX A., Table 34. and Table 35. for a full listing of the Block Addresses.
M50FLW080A, M50FLW080B
SIGNAL DESCRIPTIONSThere are two distinct bus interfaces available on
this device. The active interface is selected before
power-up, or during Reset, using the Interface
Configuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub/Low Pin Count (FWH/LPC) Signal
Descriptions section and the Address/Address
Multiplexed (A/A Mux) Signal Descriptions sec-
tion, respectively, while the supply signals are dis-
cussed in the Supply Signal Descriptions section.
Firmware Hub/Low Pin Count (FWH/LPC)
Signal DescriptionsPlease see Figure 2. and Table 1..
Input/Output Communications (FWH0/LAD0-
FWH3/LAD3). All Input and Output Communica-
tions with the memory take place on these pins.
Addresses and Data for Bus Read and Bus Write
operations are encoded on these pins.
(FWH4/
LFRAME). The Input Communication Frame
(FWH4/LFRAME) signal indicates the start of a
bus operation. When Input Communication Frame
is Low, VIL, on the rising edge of the Clock, a new
bus operation is initiated. If Input Communication
Frame is Low, VIL, during a bus operation then the
operation is aborted. When Input Communication
Frame is High, VIH, the current bus operation is ei-
ther proceeding or the bus is idle.
Identification Inputs (ID0-ID3). Up to 16 memo-
ries can be addressed on a bus, in the Firmware
Hub (FWH) mode. The Identification Inputs allow
each device to be given a unique 4-bit address. A
‘0’ is signified on a pin by driving it Low, VIL, or
leaving it floating (since there is an internal pull-
down resistor, with a value of RIL). A ‘1’ is signified
on a pin by driving it High, VIH (and there will be a
leakage current of ILI2 through the pin).
By convention, the boot memory must have ad-
dress ‘0000’, and all additional memories are giv-
en addresses, allocated sequentially, from ‘0001’.
In the Low Pin Count (LPC) mode, the identifica-
tion Inputs (ID2-ID3) can address up to 4 memo-
ries on a bus. In the LPC mode, the ID0 and ID1
signals are Reserved for Future Use (RFU). The
value on address A20-A21 is compared to the
hardware strapping on the ID2-ID3 lines to select
the memory that is being addressed. For an ad-
dress bit to be ‘1’, the corresponding ID pin can be
left floating or driven Low, VIL (again, with the in-
ternal pull-down resistor, with a value of RIL). For
an address bit to be ‘0’, the corresponding ID pin
must be driven High, VIH (and there will be a leak-
age current of ILI2 through the pin, as specified in
Table 24.). For details, see Table 5..
General Purpose Inputs (GPI0-GPI4). The
General Purpose Inputs can be used as digital in-
puts for the CPU to read, with their contents being
available in the General Purpose Inputs Register.
The pins must have stable data throughout the en-
tire cycle that reads the General Purpose Input
Register. These pins should be driven Low, VIL, or
High, VIH, and must not be left floating.
Interface Configuration (IC). The Interface Con-
figuration input selects whether the FWH/LPC in-
terface or the Address/Address Multiplexed (A/A
Mux) Interface is used. The state of the Interface
Configuration, IC, should not be changed during
operation of the memory device, except for select-
ing the desired interface in the period before pow-
er-up or during a Reset.
To select the FWH/LPC Interface, the Interface
Configuration pin should be left to float or driven
Low, VIL. To select the Address/Address Multi-
plexed (A/A Mux) Interface, the pin should be driv-
en High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
current of ILI2 through each pin when pulled to VIH.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the device. When Interface
Reset (RP) is driven Low, VIL, the memory is in
Reset mode (the outputs go to high impedance,
and the current consumption is minimized). When
RP is driven High, VIH, the device is in normal op-
eration. After exiting Reset mode, the memory en-
ters Read mode.
CPU Reset (INIT). The CPU Reset, INIT, signal
is used to Reset the device when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0/LAD0-FWH3/LAD3.
The Clock conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock in-
put is used to prevent the Top Block (Block 15)
from being changed. When Top Block Lock, TBL,
is driven Low, VIL, program and erase operations
in the Top Block have no effect, regardless of the
state of the Lock Register. When Top Block Lock,
TBL, is driven High, VIH, the protection of the Block
is determined by the Lock Registers. The state of
Top Block Lock, TBL, does not affect the protec-
tion of the Main Blocks (Blocks 0 to 14). For de-
tails, see APPENDIX A..
Top Block Lock, TBL, must be set prior to a pro-
gram or erase operation being initiated, and must
not be changed until the operation has completed,
otherwise unpredictable results may occur. Simi-
larly, unpredictable behavior is possible if WP is
11/53
M50FLW080A, M50FLW080Bchanged during Program or Erase Suspend, and
care should be taken to avoid this.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 14)
from being changed. When Write Protect, WP, is
driven Low, VIL, Program and Erase operations in
the Main Blocks have no effect, regardless of the
state of the Lock Register. When Write Protect,
WP, is driven High, VIH, the protection of the Block
or Sector is determined by the Lock Registers. The
state of Write Protect, WP, does not affect the pro-
tection of the Top Block (Block 15). For details,
see APPENDIX A..
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated, and must not be
changed until the operation has completed other-
wise unpredictable results may occur. Similarly,
unpredictable behavior is possible if WP is
changed during Program or Erase Suspend, and
care should be taken to avoid this.
Reserved for Future Use (RFU). Reserved for
Future Use (RFU). These pins do not presently
have assigned functions. They must be left discon-
nected, except for ID0 and ID1 (when in LPC
mode) which can be left connected. The electrical
characteristics for these signals are as described
in the “Identification Inputs (ID0-ID3).” section.
Address/Address Multiplexed (A/A Mux)
Signal DescriptionsPlease see Figure 3. and Table 2..
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A19). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs hold the data that is to be written to
or read from the memory. They output the data
stored at the selected address during a Bus Read
operation. During Bus Write operations they carry
the commands that are sent to the Command In-
terface of the internal state machine. The Data In-
puts/Outputs, DQ0-DQ7, are latched during a Bus
Write operation.
Output Enable (G). The Output Enable signal, G,
controls the output buffers during a Bus Read op-
eration.
Write Enable (W). The Write Enable signal, W,
controls the Bus Write operation of the Command
Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs are to be latched into the Row Ad-
dress bits (A0-A10) or the Column Address bits
(A11-A19). The Row Address bits are latched on
the falling edge of RC whereas the Column Ad-
dress bits are latched on its rising edge.
Supply Signal DescriptionsThe Supply Signals are the same for both interfac-
es.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (read, pro-
gram, erase, etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This is to prevent Bus Write operations from
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time, the operation aborts, and the memory
contents that were being altered will be invalid. Af-
ter VCC becomes valid, the Command Interface is
reset to Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents re-
quired during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Pro-
gram (see the Quadruple Byte Program command
description in A/A Mux interface and the Double/
Quadruple Byte Program command description in
FWH mode) and Fast Erase options of the memo-
ry.
When VPP = VCC, program and erase operations
take place as normal. When VPP = VPPH, Fast Pro-
gram and Erase operations are used. Any other
voltage input to VPP will result in undefined behav-
ior, and should not be used.
VPP should not be set to VPPH for more than hours during the life of the memory.
VSS Ground. VSS is the reference for all the volt-
age measurements.
M50FLW080A, M50FLW080B
Table 5. Memory Identification Input Configuration (LPC mode)
BUS OPERATIONSThe two interfaces, A/A Mux and FWH/LPC, sup-
port similar operations, but with different bus sig-
nals and timings. The Firmware Hub/Low Pin
Count (FWH/LPC) Interface offers full functional-
ity, while the Address/Address Multiplexed (A/A
Mux) Interface is orientated for erase and program
operations.
See the sections below, The Firmware Hub/Low
Pin Count (FWH/LPC) Bus Operations and Ad-
dress/Address Multiplexed (A/A Mux) Bus Opera-
tions, for details of the bus operations on each
interface.
Firmware Hub/Low Pin Count (FWH/LPC) Bus
OperationsThe M50FLW080 automatically identifies the type
of FWH/LPC protocol from the first received nibble
(START nibble) and decodes the data that it re-
ceives afterwards, according to the chosen FWH
or LPC mode. The Firmware Hub/Low Pin Count
(FWH/LPC) Interface consists of four data signals
(FWH0/LAD0-FWH3/LAD3), one control line
(FWH4/LFRAME) and a clock (CLK).
Protection against accidental or malicious data
corruption is achieved using two additional signals
(TBL and WP). And two reset signals (RP and
INIT) are available to put the memory into a known
state.
The data, control and clock signals are designed
to be compatible with PCI electrical specifications.
The interface operates with clock speeds of up to
33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations are used to read
from the memory cells, specific registers in the
Command Interface or Firmware Hub/Low Pin
Count Registers. A valid Bus Read operation
starts on the rising edge of the Clock signal when
the Input Communication Frame, FWH4/
LFRAME, is Low, VIL, and the correct Start cycle
is present on FWH0/LAD0-FWH3/LAD3. On sub-
sequent clock cycles the Host will send to the
memory: ID Select, Address and other control bits on
FWH0-FWH3 in FWH mode. Type+Dir Address and other control bits on
LAD0-LAD3 in LPC mode.
The device responds by outputting Sync data until
the wait states have elapsed, followed by Data0-
Data3 and Data4-Data7.
See Table 6. and Table 8., and Figure 7. and Fig-
ure 9., for a description of the Field definitions for
each clock cycle of the transfer. See Table 26.,
and Figure 15., for details on the timings of the sig-
nals.
Bus Write. Bus Write operations are used to write
to the Command Interface or Firmware Hub/Low
Pin Count Registers. A valid Bus Write operation
starts on the rising edge of the Clock signal when
Input Communication Frame, FWH4/LFRAME, is
Low, VIL, and the correct Start cycle is present on
FWH0/LAD0-FWH3/LAD3. On subsequent Clock
cycles the Host will send to the memory: ID Select, Address, other control bits, Data0-
Data3 and Data4-Data7 on FWH0-FWH3 in
FWH mode. Cycle Type + Dir, Address, other control bits,
Data0-Data3 and Data4-Data7 on LAD0-
LAD3.
The device responds by outputting Sync data until
the wait states have elapsed.
See Table 7. and Table 9., and Figure 8. and Fig-
ure 10., for a description of the Field definitions for
each clock cycle of the transfer. See Table 26.,
and Figure 15., for details on the timings of the sig-
nals.
Bus Abort. The Bus Abort operation can be used
to abort the current bus operation immediately. A
Bus Abort occurs when FWH4/LFRAME is driven
Low, VIL, during the bus operation. The device
puts the Input/Output Communication pins,
FWH0/LAD0-FWH3/LAD3, to high impedance.
13/53
M50FLW080A, M50FLW080BNote that, during a Bus Write operation, the Com-
mand Interface starts executing the command as
soon as the data is fully received. A Bus Abort dur-
ing the final TAR cycles is not guaranteed to abort
the command. The bus, however, will be released
immediately.
Standby. When FWH4/LFRAME is High, VIH, the
device is put into Standby mode, where FWH0/
LAD0-FWH3/LAD3 are put into a high-impedance
state and the Supply Current is reduced to the
Standby level, ICC1.
Reset. During the Reset mode, all internal circuits
are switched off, the device is deselected, and the
outputs are put to high-impedance. The device is
in the Reset mode when Interface Reset, RP, or
CPU Reset, INIT, is driven Low, VIL. RP or INIT
must be held Low, VIL, for tPLPH. The memory re-
verts to the Read mode upon return from the Re-
set mode, and the Lock Registers return to their
default states regardless of their states before Re-
set. If RP or INIT goes Low, VIL, during a Program
or Erase operation, the operation is aborted and
the affected memory cells no longer contain valid
data. The device can take up to tPLRH to abort a
Program or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
OperationsThe Address/Address Multiplexed (A/A Mux) Inter-
face has a more traditional-style interface. The sig-
nals consist of a multiplexed address signals (A0-
A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Inter-
face is included for use by Flash Programming
equipment for faster factory programming. Only a
subset of the features available to the Firmware
Hub (FWH)/Low Pin Count (LPC) Interface are
available; these include all the Commands but ex-
clude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected, all the blocks are unprotect-
ed. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to read
the contents of the Memory Array, the Electronic
Signature or the Status Register. A valid Bus Read
operation begins by latching the Row Address and
Column Address signals into the memory using
the Address Inputs, A0-A10, and the Row/Column
Address Select RC. Write Enable (W) and Inter-
face Reset (RP) must be High, VIH, and Output
Enable, G, Low, VIL. The Data Inputs/Outputs will
output the value, according to the timing con-
straints specified in Figure 17., and Table 28..
Bus Write. Bus Write operations are used to write
to the Command Interface. A valid Bus Write oper-
ation begins by latching the Row Address and Col-
umn Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column Ad-
dress Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Inter-
face Reset, RP, must be High, VIH; and Write En-
able, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write En-
able, W. See Figure 18., and Table 29., for details
of the timing requirements.
Output Disable. The data outputs are high-im-
pedance when the Output Enable, G, is at VIH.
Reset. During the Reset mode, all internal circuits
are switched off, the device is deselected, and the
outputs are put at high-impedance. The device is
in the Reset mode when RP is Low, VIL. RP must
be held Low, VIL for tPLPH. If RP goes Low, VIL,
during a Program or Erase operation, the opera-
tion is aborted, and the affected memory cells no
longer contain valid data. The memory can take up
to tPLRH to abort a Program or Erase operation.
M50FLW080A, M50FLW080B
15/53
M50FLW080A, M50FLW080B
M50FLW080A, M50FLW080B
17/53
M50FLW080A, M50FLW080B
M50FLW080A, M50FLW080B
COMMAND INTERFACEAll Bus Write operations to the device are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings, and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time to monitor
the progress or the result of the operation.
The Command Interface reverts to the Read mode
when power is first applied, or when exiting from
Reset. Command sequences must be followed ex-
actly. Any invalid combination of commands will be
ignored. See Table 11. for the available Command
Codes.
Table 11. Command CodesThe following commands are the basic commands
used to read from, write to, and configure the de-
vice. The following text descriptions should be
read in conjunction with Table 13..
Read Memory Array Command. The Read
Memory Array command returns the device to its
Read mode, where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
device to Read mode. Once the command is is-
sued, the device remains in Read mode until an-
other command is issued. From Read mode, Bus
Read operations access the memory array.
If the Program/Erase Controller is executing a Pro-
gram or Erase operation, the device will not accept
any Read Memory Array commands until the oper-
ation has completed.
For a multibyte read, in the FWH mode, the ad-
dress, that was transmitted with the command, will
be automatically aligned, according to the MSIZE
granularity. For example, if MSIZE=7, regardless
of any values that are provided for A6-A0, the first
output will be from the location for which A6-A0 are
all ‘0’s.
Read Status Register Command. The Read
Status Register command is used to read the Sta-
tus Register. One Bus Write cycle is required to is-
sue the Read Status Register command. Once the
command is issued, subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Signature Command. The
Read Electronic Signature command is used to
read the Manufacturer Code and the Device Code.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once the com-
mand is issued, the Manufacturer Code and De-
vice Code can be read using conventional Bus
Read operations, and the addresses shown in Ta-
ble 12..
Table 12. Electronic Signature CodesNote:1. A22 should be ‘1’, and the ID lines and upper address bits
should be set according to the rules illustrated in Table 5.,
Table 6. and Table 8..
The device remains in this mode until another
command is issued. That is, subsequent Bus
Read operations continue to read the Manufactur-
er Code, or the Device Code, and not the Memory
Array.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time.
The Program command works by changing appro-
priate bits from ‘1’ to ‘0’. (It cannot change a bit
from ‘0’ back to ‘1’. Attempting to do so will not
modify the value of the bit. Only the Erase com-
mand can set bits back to ‘1’. and does so for all of
the bits in the block.)
Two Bus Write operations are required to issue the
Program command. The second Bus Write cycle
latches the address and data, and starts the Pro-
gram/Erase Controller.
19/53
M50FLW080A, M50FLW080BOnce the command is issued, subsequent Bus
Read operations read the value in the Status Reg-
ister. (See the section on the Status Register for
details on the definitions of the Status Register
bits.)
If the address falls in a protected block, the Pro-
gram operation will abort, the data in the memory
array will not be changed, and the Status Register
will indicate the error.
During the Program operation, the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands are ignored.
See Figure 22., for a suggested flowchart on using
the Program command. Typical Program times are
given in Table 18..
Quadruple Byte Program Command (A/A Mux
Interface). The Quadruple Byte Program Com-
mand is used to program four adjacent Bytes in
the memory array at a time. The four Bytes must
differ only for addresses A0 and A1. Programming
should not be attempted when VPP is not at VPPH.
Five Bus Write operations are required to issue the
command. The second, third and fourth Bus Write
cycles latch the respective addresses and data of
the first, second and third Bytes in the Program/
Erase Controller. The fifth Bus Write cycle latches
the address and data of the fourth Byte and starts
the Program/Erase Controller. Once the command
is issued, subsequent Bus Read operations read
the value in the Status Register. (See the section
on the Status Register for details on the definitions
of the Status Register bits.)
During the Quadruple Byte Program operation, the
memory will only accept the Read Status Register
and Program/Erase Suspend commands. All other
commands are ignored.
Note that the Quadruple Byte Program command
cannot change a bit set to ‘0’ back to ‘1’ and at-
tempting to do so will not modify its value. One of
the erase commands must be used to set all of the
bits in the block to ‘1’.
See Figure 24., for a suggested flowchart on using
the Quadruple Byte Program command. Typical
Quadruple Byte Program times are given in Table
Double/Quadruple Byte Program Command
(FWH Mode). The Double/Quadruple Byte Pro-
gram Command can be used to program two/four
adjacent Bytes to the memory array at a time. The
two Bytes must differ only for address A0; the four
Bytes must differ only for addresses A0 and A1.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
start address and two/four data Bytes and starts
the Program/Erase Controller. Once the command
is issued, subsequent Bus Read operations read
the contents of the Status Register. (See the sec-
tion on the Status Register for details on the defi-
nitions of the Status Register bits.)
During the Double/Quadruple Byte Program oper-
ation the memory will only accept the Read Status
register and Program/Erase Suspend commands.
All other commands are ignored.
Note that the Double/Quadruple Byte Program
command cannot change a bit set to ‘0’ back to ‘1’
and attempting to do so will not modify its value.
One of the erase commands must be used to set
all of the bits in the block to ‘1’.
See Figure 23., for a suggested flowchart on using
the Double/Quadruple Byte Program command.
Typical Double/Quadruple Byte Program times
are given in Table 18..
Chip Erase Command. The Chip Erase Com-
mand erases the entire memory array, setting all
of the bits to ‘1’. All previous data in the memory
array are lost. This command, though, is only
available under the A/A Mux interface.
Two Bus Write operations are required to issue the
command, and to start the Program/Erase Con-
troller. Once the command is issued, subsequent
Bus Read operations read the contents of the Sta-
tus Register. (See the section on the Status Reg-
ister for details on the definitions of the Status
Register bits.)
Erasing should not be attempted when VPP is not
at VPPH, otherwise the result is uncertain.
During the Chip Erase operation, the memory will
only accept the Read Status Register command.
All other commands are ignored.
See Figure 26., for a suggested flowchart on using
the Chip Erase command. Typical Chip Erase
times are given in Table 18..
Block Erase Command. The Block Erase com-
mand is used to erase a block, setting all of the bits
to ‘1’. All previous data in the block are lost.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
block address and starts the Program/Erase Con-
troller. Once the command is issued, subsequent
Bus Read operations read the contents of the Sta-
tus Register. (See the section on the Status Reg-
ister for details on the definitions of the Status
Register bits.)
If the block, or if at least one sector of the block (for
the blocks that are split into sectors), is protected
(FWH/LPC only) then the Block Erase operation
will abort, the data in the block will not be changed,
and the Status Register will indicate the error.
During the Block Erase operation the memory will
only accept the Read Status Register and Pro-
gram/Erase Suspend commands. All other com-
mands are ignored.
M50FLW080A, M50FLW080BSee Figure 27., for a suggested flowchart on using
the Block Erase command. Typical Block Erase
times are given in Table 18..
Sector Erase Command. The Sector Erase
command is used to erase a Uniform 4-KByte Sec-
tor, setting all of the bits to ‘1’. All previous data in
the sector are lost.
Two Bus Write operations are required to issue the
command. The second Bus Write cycle latches the
Sector address and starts the Program/Erase
Controller. Once the command is issued, subse-
quent Bus Read operations read the contents of
the Status Register. (See the section on the Status
Register for details on the definitions of the Status
Register bits.)
If the Sector is protected (FWH/LPC only), the
Sector Erase operation will abort, the data in the
Sector will not be changed, and the Status Regis-
ter will indicate the error.
During the Sector Erase operation the memory will
only accept the Read Status Register and Pro-
gram/Erase Suspend commands. All other com-
mands are ignored.
See Figure 27., for a suggested flowchart on using
the Sector Erase Command. Typical Sector Erase
times are given in Table 18..
Clear Status Register Command. The Clear
Status Register command is used to reset Status
Register bits SR1, SR3, SR4 and SR5 to ‘0’. One
Bus Write is required to issue the command. Once
the command is issued, the device returns to its
previous mode, subsequent Bus Read operations
continue to output the data from the same area, as
before.
Once set, these Status Register bits remain set.
They do not automatically return to ‘0’, for exam-
ple, when a new program or erase command is is-
sued. If an error has occurred, it is essential that
any error bits in the Status Register are cleared, by
issuing the Clear Status Register command, be-
fore attempting a new program or erase com-
mand.
Program/Erase Suspend Command. The Pro-
gram/Erase Suspend command is used to pause
the Program/Erase Controller during a program or
Sector/Block Erase operation. One Bus Write cy-
cle is required to issue the command.
Once the command has been issued, it is neces-
sary to poll the Program/Erase Controller Status
bit until the Program/Erase Controller has paused.
No other commands are accepted until the Pro-
gram/Erase Controller has paused. After the Pro-
gram/Erase Controller has paused, the device
continues to output the contents of the Status Reg-
ister until another command is issued.
During the polling period, between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing, it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit indicates that the Program/
Erase Controller is no longer active, the Program
Suspend Status bit or the Erase Suspend Status
bit can be used to determine if the operation has
completed or is suspended.
During Program/Erase Suspend, the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume com-
mands will be accepted by the Command Inter-
face. Additionally, if the suspended operation was
Sector Erase or Block Erase then the program
command will also be accepted. However, it
should be noted that only the Sectors/Blocks not
being erased may be read or programmed correct-
ly.
See Figure 25., and Figure 28., for suggested
flowcharts on using the Program/Erase Suspend
command. Typical times and delay durations are
given in Table 18..
Program/Erase Resume Command. The Pro-
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the command.
Once the command is issued, subsequent Bus
Read operations read the contents of the Status
Register.
21/53
M50FLW080A, M50FLW080B
Table 13. CommandsNote:1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read Electronic
Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles are WRITE.
BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC mode), and
A21 and A20 are set according to the rules shown in Table 5. (for LPC mode) After a Read Memory Array command, read the memory as normal until another command is issued. After a Read Status Register command, read the Status Register as normal until another command is issued. After the erase and program commands read the Status Register until the command completes and another command is issued. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during Erase
Suspend) and Program/Erase Resume commands can be issued. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status Register until
the Program/Erase Controller completes and the memory returns to Read Mode. Do not use Invalid or Reserved commands. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t Care. PD is
two or four Bytes depending on Msize code.
10. “1+” indicates that there is one write cycle, followed by any number of read cycles.
11. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read Operation
is all that is needed.
12. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.
M50FLW080A, M50FLW080B
STATUS REGISTERThe Status Register provides information on the
current or previous Program or Erase operation.
The bits in the Status Register convey specific in-
formation about the progress of the operation.
To read the Status Register, the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any ad-
dress.
The text descriptions, below, should be read in
conjunction with Table 14., where the meanings of
the Status Register bits are summarized.
Program/Erase Controller Status (Bit SR7).This bit indicates whether the Program/Erase Con-
troller is active or inactive. When the Program/
Erase Controller Status bit is ‘0’, the Program/
Erase Controller is active; when the bit is ‘1’, the
Program/Erase Controller is inactive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued, until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses,
the bit is ‘1’.
The end of a Program and Erase operation can be
found by polling the Program/Erase Controller
Status bit can be polled. The other bits in the Sta-
tus Register should not be tested until the Pro-
gram/Erase Controller has completed the
operation (and the Program/Erase Controller Sta-
tus bit is ‘1’).
After the Program/Erase Controller has completed
its operation, the Erase Status, Program Status,
VPP Status and Block/Sector Protection Status
bits should be tested for errors.
Erase Suspend Status (Bit SR6). This bit indi-
cates that an Erase operation has been suspend-
ed, and that it is waiting to be resumed. The Erase
Suspend Status should only be considered valid
when the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive). After a Pro-
gram/Erase Suspend command is issued, the
memory may still complete the operation rather
than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’, the Pro-
gram/Erase Controller is active or has completed
its operation. When the bit is ‘1’, a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is is-
sued, the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit SR5). This bit indicates if a
problem has occurred during the erasing of a Sec-
tor or Block. The Erase Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Erase Status bit is ‘0’, the memory has
successfully verified that the Sector/Block has
been erased correctly. When the Erase Status bit
is ‘1’, the Program/Erase Controller has applied
the maximum number of pulses to the Sector/
Block and still failed to verify that the Sector/Block
has been erased correctly.
Once the Erase Status bit is set to ‘1’, it can only
be reset to ‘0’ by a Clear Status Register com-
mand, or by a hardware reset. If it is set to ‘1’, it
should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to have failed, too.
Program Status (Bit SR4). This bit indicates if a
problem has occurred during the programming of
a byte. The Program Status bit should be read
once the Program/Erase Controller Status bit is ‘1’
(Program/Erase Controller inactive).
When the Program Status bit is ‘0’, the memory
has successfully verified that the byte has been
programmed correctly. When the Program Status
bit is ‘1’, the Program/Erase Controller has applied
the maximum number of pulses to the byte and still
failed to verify that the byte has been programmed
correctly.
Once the Program Status bit is set to ‘1’, it can only
be reset to ‘0’ by a Clear Status Register com-
mand, or by a hardware reset. If it is set to ‘1’, it
should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to have failed, too.
VPP Status (Bit SR3). This bit indicates whether
an invalid voltage was detected on the VPP pin at
the beginning of a Program or Erase operation.
The VPP pin is only sampled at the beginning of
the operation. Indeterminate results can occur if
VPP becomes invalid during a Program or Erase
operation.
Once the VPP Status bit set to ‘1’, it can only be re-
set to ‘0’ by a Clear Status Register command, or
by a hardware reset. If it is set to ‘1’, it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
have failed, too.
Program Suspend Status (Bit SR2). This bit in-
dicates that a Program operation has been sus-
pended, and that it is waiting to be resumed. The
Program Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is ‘1’ (Program/Erase Controller inactive).
After a Program/Erase Suspend command is is-
sued, the memory may still complete the operation
instead of entering the Suspend mode.
23/53
M50FLW080A, M50FLW080BWhen the Program Suspend Status bit is ‘0’, the
Program/Erase Controller is active, or has com-
pleted its operation. When the bit is ‘1’, a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command.
When a Program/Erase Resume command is is-
sued, the Program Suspend Status bit returns to
‘0’.
Block/Sector Protection Status (Bit SR1). The
Block/Sector Protection Status bit can be used to
identify if the Program or Erase operation has tried
to modify the contents of a protected block or sec-
tor. When the Block/Sector Protection Status bit is
reset to ‘0’, no Program or Erase operations have
been attempted on protected blocks or sectors
since the last Clear Status Register command or
hardware reset. When the Block/Sector Protection
Status bit is ‘1’, a Program or Erase operation has
been attempted on a protected block or sector.
Once it is set to ‘1’, the Block/Sector Protection
Status bit can only be reset to ‘0’ by a Clear Status
Register command or by a hardware reset. If it is
set to ‘1’, it should be reset before a new Program
or Erase command is issued, otherwise the new
command will appear to have failed, too.
Using the A/A Mux Interface, the Block/Sector Pro-
tection Status bit is always ‘0’.
Reserved (Bit SR0). Bit 0 of the Status Register
is reserved. Its value should be masked.
Table 14. Status Register BitsNote:1. For Program operations during Erase Suspend, the SR6 bit is ‘1’, otherwise the SR6 bit is ‘0’.
M50FLW080A, M50FLW080B
FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION
REGISTERSWhen the Firmware Hub Interface/Low Pin Count
is selected, several additional registers can be ac-
cessed. These registers control the protection sta-
tus of the Blocks/Sectors, read the General
Purpose Input pins and identify the memory using
the manufacturer code. See Table 15. for the
memory map of the Configuration Registers. The
Configuration registers are accessed directly with-
out using any specific command code. A single
Bus Write or Bus Read Operation, with the appro-
priate address (including A22=0), is all that is
needed.
Lock RegistersThe Lock Registers control the protection status of
the Blocks/Sectors. Each Block/Sector has its own
Lock Register. Three bits within each Lock Regis-
ter control the protection of each Block/Sector: the
Write Lock Bit, the Read Lock Bit and the Lock
Down Bit.
The Lock Registers can be read and written. Care
should be taken, though, when writing. Once the
Lock Down Bit is set, ‘1’, further modifications to
the Lock Register cannot be made until it is
cleared again by a reset or power-up.
See Table 16. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block/Sector can be
modified (using the Program or Erase Command).
When the Write Lock Bit is set, ‘1’, the Block/Sec-
tor is write protected – any operations that attempt
to change the data in the Block/Sector will fail, and
the Status Register will report the error. When the
Write Lock Bit is reset, ‘0’, the Block/Sector is not
write protected by the Lock Register, and may be
modified, unless it is write protected by some other
means.
If the Top Block Lock signal, TBL, is Low, VIL, then
the Top Block (Block 15) is write protected, and
cannot be modified. Similarly, if the Write Protect
signal, WP, is Low, VIL, then the Main Blocks
(Blocks 0 to 14) are write protected, and cannot be
modified. For details, see APPENDIX A. and Table
After power-up, or reset, the Write Lock Bit is al-
ways set to ‘1’ (write-protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block/Sector can be
read (in Read mode). When the Read Lock Bit is
set, ‘1’, the Block/Sector is read protected – any
operation that attempts to read the contents of the
Block/Sector will read 00h instead. When the
Read Lock Bit is reset, ‘0’, read operations are al-
lowed in the Block/Sector, and return the value of
the data that had been programmed in the Block/
Sector.
After power-up, or reset, the Read Lock Bit is al-
ways reset to ‘0’ (not read-protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset, or power-up, is required be-
fore changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
Table 15. Configuration Register MapNote: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address
bits should be set according to the rules shown in the ADDR field of Table 6. to Table 9..
25/53
M50FLW080A, M50FLW080B
Table 16. Lock Register Bit DefinitionsNote:1. Applies to the registers that are defined in Table 34. and Table 35..
Table 17. General Purpose Inputs Register DefinitionNote:1. Applies to the General Purpose Inputs Register (GPI-REG).
Firmware Hub/Low Pin Count (FWH/LPC)
General Purpose Input RegisterThe FWH/LPC General Purpose Input Register
holds the state of the General Purpose Input pins,
GPI0-GPI4. When this register is read, the state of
these pins is returned. This register is read-only.
Writing to it has no effect.
The signals on the FWH/LPC Interface General
Purpose Input pins should remain constant
throughout the whole Bus Read cycle.
Manufacturer Code RegisterReading the Manufacturer Code Register returns
the value 20h, which is the Manufacturer Code for
STMicroelectronics. This register is read-only.
Writing to it has no effect.
M50FLW080A, M50FLW080B
PROGRAM AND ERASE TIMESThe Program and Erase times are shown in Table
Table 18. Program and Erase Times
Note:1. TA = 25°C, VCC = 3.3V Sampled only, not 100% tested. Time to program two Bytes. Time to program four Bytes. Time obtained executing the Quadruple Byte Program command.
27/53
M50FLW080A, M50FLW080B
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 19. Absolute Maximum RatingsNote:1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for
less than 20ns during transitions. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
