M491B1 Fast Delivery |IC PHOENIX CO.,LIMITED

M491B1 ,SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM WITH 1 ANALOG CONTROLELECTRICAL CHARACTERISTICS(T = 0 to + 70°C, V = +5V unless otherwise specified)amb DDPin Symbol Par ..
M491B1 ,SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM WITH 1 ANALOG CONTROLM491BSINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEMWITH 1 ANALOG CONTROL.16-STATION MEMORY - 7-SEGMENT ..
M494B1 ,Single-chip voltage tuning system with 4 analog controls and uP interfaceM494SINGLE-CHIP VOLTAGE TUNING SYSTEM WITH4 ANALOG CONTROLS AND μP INTERFACE.NON-VOLATILE MEMORY FO ..
M4N26 ,6-Pin DIP Optoisolators Transistor Output
M4N37 ,6-Pin DIP Optoisolators Transistor Output
M4T28-BR12SH ,TIMEKEEPER SNAPHAT Battery & CrystalAbsolute Maximum Ratings . 7DC and AC PARAMETERS . . 8Table 3. DC and AC Measurement Co ..
M62009P , LOW POWER 2 OUTPUT SYSTEM RESET IC WITH EXTERNAL INPUT
M62016FP , Low Power 2 Output System Reset IC
M62016FP , Low Power 2 Output System Reset IC
M62021 , SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP
M62023FP , System Reset IC with Switch for 3V Memory Back-up
M62023FP , System Reset IC with Switch for 3V Memory Back-up

M491B1
SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM WITH 1 ANALOG CONTROL
M491B
SINGLE-CHIP VOL TAGE SYNTHESIS TUNING SYSTEM
WITH1 ANALOG CONTROL
September 1992 16-STATION MEMORY- 7-SEGMENT LED
DISPLAY. VOLTAGESYNTHESIZER: 13 BITS. 4-BAND PRESET CAPABILITY. NON-VOLATILE MEMORY: 304 BITS 16 WORDS OF19 BITS FOR TUNING VOLT-
AGE (13 bits)- BAND(2 bits)- FINE DETUN-
ING(4 bits) 104 MODIFY CYCLES PER WORD MIN10 YEARS DATA RETENTION. PCM REMOTE CONTROL RECEIVER: DE-
CODES SIGNAL TRANSMITTED BY M708. VOLUME D/A: 6-BIT RESOLUTION/ 8kHz. MEMORY SKIP FUNCTION. AUTOMATIC SEARCH WITH DIGITAL AFT
CONTROL. FINE DETUNING D/A ACTING ON AFT DIS-
CRIMINA TOR (16 steps) WITH SEPARATE
STORAGE FOR EACH MEMORY POSITION.
ALTERNATIVELYIT CAN BE USED TO CON-
TROL BRIGHTNESS OR COLOUR SATURA-
TION. MANUAL SEARCH WITH DIGITAL AFT CON-
TROL. MANUAL SEARCH WITH LINEAR AFT. SWEEP SEARCHDISPLAYOUTPUT. SUPPLYVOLTAGES: VDD=+ 5V,
VPP=+ 25V FOR THE MEMORY. CLOCK OSCILLATOR: 445TO 510kHz. INTEGRATED DIGITAL POWER ON RESET
(no external initialization circuitry required)
DIP40
(Plastic Package)
ORDER CODE: M491B1
DESCRIPTION
The M491Bisa monolithic N-MOS LSI circuitin-
cludinga Floating-gate Non-Volatile Memory for
storageofupto16 stations. Tuningof the station performedwitha 8192 step D/Aconverter, using
the principleof voltage synthesis.Itis designedfor
7-segmentLED displays. Direct memory selection possibleonly from remotecontrol while Up/Down
memory scanningis possibleon the set and also
from remote control. An option input for8or 16
stationsis available. The circuit also includesa
PCM remote control receiver operatingin conjunc-
tion with the transmitter M708. The highly reliable
transmission code ensureserror-free signaldetec-
tion evenin presenceof high noise conditions.
Searchof the stationis possiblein automaticor
manual modes. The circuit can operate witha
Digitalor LinearAFT control.TheDigitalAFTmode necessaryfor automatic search and requiresan
external circuit (TDA4433or equivalent, e.g. dual
comparator plus TV station detector)to convertthe
AFC-S-curve intoan Up/Down command. Fine tun-
ing (detuning)is also possible with different modes
ofoperation.Thecircuitis assembledin 40-pindual
in-line plastic package.
(GND)
MEMORYSUPPLY
MEMORYTIMING
FINETUNINGD/A
TUNINGD/A
DIGITALAFTSTATUS
OSC.IN
OSC.OUT
TEST
AFT1
AFT2
SWEEPDISPLAYOUT
VOLUMED/A
DIGITALAFTEN. X4
MAINSON OPTION
MAINSON/OFF
SEGM.a
SEGM.b
SEGM.c
SEGM.d
OPT.8/16
SEGM.e
SEGM.f
SEGM.g
SEGM.h+i
UHF
CATV
VHFIII
VHFI
VSSVDD
VSS
(GND)
LINEARAFTDEF.
I.R.INPUT
491B-01.EPS
PIN CONNECTIONS
1/16
M491B532383940
TDA2320
M708
10MHz
OSCOUT
TEST
510MHz
(25V)
OPT.
8/16
TUNING
D/A
FINE
TUNING
D/A 13 151617 252628293033343536
VHF
VHF
III
CAT
UHF AFT1 AFT2
SWEEP
DISPLAY
OUT
DIGITAL
AFT
STATUS
DIGITAL
AFT
ENABLE
LINEAR
AFT
DEFEAT
VOLUME
D/A
MAINS
ON/OFF
MAINS
OPTION
BAND
OUT
AUTO
SEARCH
STOP
DIGITAL
AFT
13.2V(AFT1) (AFT2)DOWN
+12Vbcdefg
AFC-S
curve
491B-02.EPS
FUNCTIONAL DIAGRAM
M491B
2/16
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VDD Supply Voltage – 0.3,+7 V
VPP Memory Supply Voltage – 0.3,+26 V Input Voltage – 0.3,+15 V
VO(off) Off State Input Voltage (exceptpin3)
Pin3
IOL Output Low Current
Led Driver Outputs
Pins6–14
Pins4–5
All Other Outputs
tpd Max. Delay between Memory Timing and Memory Supply Pulses 5 μs
Ptot Total Package Power Dissipation 1 W
Tstg Storage Teperature – 25,+ 125 °C
Top Operating Temperature 0,+70 °C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage tothe device. Thisisa stress rating onlyand
functional operation ofthe device attheseorany other conditions above those indicatedin theoperational sectionsof thisspecificationisnot
implied.Exposureto absolutemaximum rating conditionsfor extended periods may affectdevice reliability.
491B-01.TBL ELECTRICAL CHARACTERISTICS
(Tamb=0to+ 70°C, VDD= +5V unless otherwise specified)
Pin Symbol Parameter Test Conditions Min. Typ. Max. Unit
2-Memory Supply IPP Memory Supply Current VPP= 25V
Write Peak
Average
Erase Peak
Average
Read Peak
Average
2.5 Pull Down Resistor 25 kΩ
3–Write Timing Out VOL Output Low Voltage VDD= 4.75V,IOL=2.5 mA 8 V(off) Output Leakage Current VDD= 4.75V, VOUT=26V 100 μA
4–Fine Tuning D/A
5–Tuning D/A(off) VDD= 5.25V,VO(off)= 13.2V 50 μA
VOL VDD= 4.75V,IOL=5 mA 1 V
6–Digital AFT Out VOL VDD= 4.75V,IOL=20 mA 1.5 V(off) VDD= 5.25V,VO(off)= 13.2V 100 μA
9–Power Supply IDD Supply Current VDD= 5.25V 100 mA
11–I.R. Input VIPP Peak-to-Peak Voltage 0.5 13.2 V
12–AFT1
13–AFT2
VIL Input low Voltage VDD= 5.25V 1.5 V
VIH Input High Voltage VDD= 5.25V 3.5 V
IIL Input Low Current VDD= 5.25V,VIL= 1.5V –0.4 mA Pull-up Resistor 30 kΩ
14—Display Out VOL VDD= 4.75V,IOL=20 mA 1.5 V(off) VDD= 5.25V,VO(off)= 13.2V 100 μA
15–Volume D/A VOL VDD= 4.75V,IOL=4 mA 1 V(off) VDD= 5.25V,VO(off)= 13.2V 50 μA
16–Linear AFT Out VOL VDD= 4.75V,IOL=1 mA 0.4 V(off) VDD= 5.25V,VO(off)= 13.2V 50 μA
17–Digital AFT En-
able
VIL 0.8 V
VIH 2.0 V
IIL VDD= 5.25V,VIL= 0.8V –0.4 mA Pull-up Resistor 30 kΩ
491B-02.TBL
M491B
3/16
ELECTRICAL CHARACTERISTICS (continued)Pin Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIL 1.5 V
VIH 3.5 V
IIL VDD= 5.25V,VIL=0.8V –0.4 mA Pull-up Resistor 30 kΩ
VOL VDD= 4.75V,IOL=1 mA 0.4 V(off) VO(off)= 5.5V 25 μA
25–MainsOn En-
able
VIL 0.8 V
VIH 2.4 V
IIL VDD= 5.25V –0.4 mA Pull-up Resistor VIL= 0.8V 30 kΩ
26–Mains On/Off VOL VDD= 4.75V,IOL= 100μA 0.4 V VDD= 4.75V,VO= 0.7V –1.6 mA
31–Z2
32–Z1
MPXfor
Display Out
VOL VDD= 4.75V,IOL=1 mA 0.4 V(off) VDD= 5.25V,VO(off)= 13.2V 50 μA
37–UHF
38–CATV
39–VHFIII
40–VHFI
VOL VDD= 4.75V,IOL=1 mA 3 V
VOH VDD= 4.75V,IOH= –150μA 2.4 V
VIL 0.3 V
VIH 3 V(off) VDD= 5.25V,VO(off)= 13.2V 50 μA
34-35 Display Out
VOL VDD= 4.75V,IOL=20 mA 1.5 V
36-Display Out VOL VDD= 4.75V,IOL=30 mA 1.5 V
31-Memory 8/16 VIH 2.0 V
VIL 0.8 V
Keyboard}
Keyboard
Out}}
491B-03.TBL
DESCRIPTION (All timingsat fclock= 500kHz)
PIN1: VSS
The substrateof theICis connectedto thispin.This the reference pinforall parametersof the IC.
PIN2: MEMORY SUPPLY VOLTAGE supply voltageof 25±1V hastobe appliedto
this pin during the modify and read cycles.
MODIFY CYCLE
Amodify cycle consistsof three steps:All ”1”s arewritten inthe bitsof theselected word.All bitsof the selected word are erased (all ”0”s) The new contentis written.
Thusa constant agingofall the bitsof the wordis
obtained.
During both write and erase cycles the memory
statusis checked continuously; therefore after
eachwriteorerasepulsea readoperationis carried
out. The writeor the erase operations are stopped soonas the resultof the read operationis valid.
WRITE CYCLE. The peakof the current flowing
through pin2 duringa write operationis shownin
fig.1, while fig.2 shows the envelopeof the same
current.
The typical write timeis 3-4 ms for the first cycles
and increasesto about30 ms after 1000 cycles.
M491B
4/16
(mA)Typ. max. 20msec Typ. max. 8msec (ms)
491B-04.EPS
Figure2
ERASE CYCLE
Figure3 shows the timing and the waveformof the
current flowing through Pin2 during the erase
operation. The peak currentis 7mA (max) during
the erase cycle and 6mA (max) during the read
cycle. The typical erase timeis 10ms fora new
device and increases with the numberof modify
operationsupto 200ms after 1000 cycles. orderto protect the memoryin caseof failureof
some bits the modify operationis stopped after
1sec.
READ CYCLE
Figure4 shows the waveformof the current during read operation.44
256μs
6mA
7mA
128μs 52
491B-05.EPS
Figure3 3244 116μs
256μs
40mA
6mA
12mA
After about 30msec
491B-03.EPS
Figure1
6mA
128μs
84μs
480μs
491B-06.EPS
Figure4
M491B
5/16
PIN3: MEMORY TIMING OUTPUT
This output gives the timing for the pulsesto be
appliedat Pin2 during the modify and read cycles.
The output consistsofan opendrain transistor.
PIN4: FINE TUNING D/A (see Figure5) D/A converter with 16-step resolution anda fre-
quencyof15kHzcanbe usedtogeneratea voltage
which,if fedtoa varicap diodein parallel tothe AFC
discriminator, will detune the receiverbya smallΔf
while maintaining the actionof the Digital AFT. This
output canbe usedin conjunction with both Linear
and Digital AFT modesof operations.
The Fine tuning function operatesas follows:At the startof any automaticor manual search,
the outputis setat the mid range. Whenthe search has been completeditis possi-
bleto operateon FT± commands.
The store command memorizes this information
together with the 13 tuning voltage bits and2
information bits. Modification timeof FT D/Aisof1 step every
200ms ifissued locallyor every2 received signals
from Remote control transmitter.
PIN5: TUNING D/A (see Figure6)213= 8192 step pulse modulated signal for the
tuning voltageis availableon this pin.
Pulse modulationis implementedby combinationa rate multiplier and pulse width principle.
Witha tuning voltage increasing from zero, the
numberof pulses increases continuously upto8= 256; starting from this point the numberof
pulses remains the same but the pulses get larger
until they reach the maximum contentof the inter-
nal counter. The output consistsofan open drain
transistor which offersa low impedanceto ground
whenin the ON state.OUT 7 FT
64μs
Mid
Range
Fine Tuning Output
491B-07.EPS
Figure5
M491B
6/16
AD/A
Converter
Varicap
down-up
491B-08.EPS
Figure6
PIN6: DIGITAL AFT STATUS OUTPUT
(see Figure7)
This output shows the statusof the digitalAFT.Itis
low when the digital AFTis enabled andit can
directly drivea LED.
The output consistsofan open drain transistor.
PINS7&8: OSCILLATOR INPUT/OUTPUT
(see Figure8)
The frequencyof the clock oscillator should be
between 445 and 510kHzusinga low-cost ceramic
resonator.In these conditions the valueof the
reference frequencyof the transmitter canbe inthe
same range.In otherwords the transmitterand the
receiver can operate with different reference fre-
quencies.
max.13.2V
491B-09.EPS
Figure7 8
455to
510kHz
100pF100pF
491B-10.EPS
Figure8
PIN9: VDD
The supply voltage hasto be comprisedin the
range 4.75to 5.25V. Whenitis appliedan internal
poweron resetof 0.5sis generated.
The memory position1is automatically readif the
mainson option input (Pin 25)is grounded.
PIN10: TEST
This pinis usedfor testing andhasto beconnected VSS.
PIN11: I.R. SIGNAL INPUT(see Figure9)
The integrated receiver decodes signals transmit-
tedby M708, address9.
The minimum signalto be appliedis 0.5V peak-to-
peak. (AC-coupled).
The receiver input section performs the following
testson the incoming signalto achieve the neces-
sary noise immunity: measurementof the pulse distance (time base
synchronization)
M491B
7/16
491B-11.EPS
Figure9
M491B C
TDA2320
orTDA8160 Supply Voltageof
TDA2320 R C
2.2kΩ
10kΩ
4.7nF
4.7nF
M491B REMOTE CONTROL RECEIVER TRUTH TABLE. Transmitter M708; Address Code9
Command
Number
I.R. Code FunctionC1 C2 C3 C4 C5 C6 0 0 0 0 0 0 Endto Transmission
Power On/Off
Mute On/Off
Memory1
Memory2
Memory3
Memory4
Fine DetuningUp
Fine Detuning Down
Memory5
Memory6
Memory7
Memory8
MemoryUp
Memory Down
Memory9
Memory10
Memory11
Memory12
Manual SearchUp
Manual Search Down
Memory13
Memory14
Memory15
Memory16
VolumeUp
Volume Down
Memory Addressing
Digital AFTOn
Band Sequential
Automatic Search Mute
491B-04.TBL checkof the positionof the received bitsopening
windowat the time bases checkof the paritybit checkof theabsenceof pulsesbetweenthe parity
bit and the stop pulse checkof noiselevel ;the receiver checksparasitic
transients inside and outside the time windows. the above test conditions are not fulfilled, the
received wordis rejected and not decoded.If the
received signalis acknowledgedasa valid wordit storedan decoded.
The endof transmission willbe acknowledgedby
receiving the endof transmissioncode orbymeans an internal timerif the transmission remains
interruptedfor more than about 550ms.
PINS12&13: AFT1-AFT2 (STOP/AFT INPUTS)
These pins are enabled during the automatic
search and during normal operation, when the
digital AFTis enabled (see descriptionof Pin 17).
The STOP/AFT inputs are also disabled internally
duringanyprogramor bandchange fortheduration the Mute signal.
M491B
8/16

Partno	Mfg	Dc	Qty	Available	Descript
M491B1	ST	N/a	200	avai	SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM WITH 1 ANALOG CONTROL
M491B1	SGS	N/a	10	avai	SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM WITH 1 ANALOG CONTROL