M48Z58Y-70MH1E ,64 Kbit (8Kb X 8) ZEROPOWER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 4. DIP Connections 5Figur ..
M48Z58Y-70MH1F ,64 Kbit (8Kb X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 6. Operating and ..
M48Z58Y-70MH6 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 6. Operating and ..
M48Z58Y-70PC1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMFEATURES SUMMARY . . . . . 1Figure 1. CAPHAT™ DIP Solution . .1Figure 2. SOIC Solution ..
M48Z58Y-70PC1. ,64 Kbit (8Kb X 8) ZEROPOWER SRAMM48Z58M48Z58Y®5V, 64 Kbit (8 Kbit x8) ZEROPOWER SRAM
M48Z58Y-70PC6 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMLogic Diagram Table 1. Signal NamesA0-A12 Address InputsVCCDQ0-DQ7 Data Inputs / Outputs13 8E Chip ..
M62005L , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M62007L , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES
M48Z58-70PC1-M48Z58Y-70MH1-M48Z58Y-70MH1E-M48Z58Y-70MH1F-M48Z58Y-70MH6-M48Z58Y-70PC1-M48Z58Y-70PC1.-M48Z58Y-70PC6
64 Kbit (8Kb X 8) ZEROPOWER SRAM
1/20November 2004
M48Z58
M48Z58Y5V, 64 Kbit (8 Kbit x8) ZEROPOWER® SRAM
FEATURES SUMMARY INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY READ CYCLE TIME EQUALS WRITE CYCLE
TIME AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage) M48Z58: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V M48Z58Y: 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE PACKAGING INCLUDES A 28-LEAD SOIC
and SNAPHAT® TOP (to be ordered
separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 8K x8 SRAMs
M48Z58, M48Z58Y
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. CAPHAT™ DIP Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. SOIC Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 13.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Outline . . . . . . . . . . . . . .14
Table 11. PMDIP28 – 28-pin Plastic DIP, battery CAPHAT™, Package Mechanical Data. . . . . . .14
Figure 14.SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline . . . . . . . .15
Table 12. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data 15
Figure 15.SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline. . . . . . . . . . . . . . .16
Table 13. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data . . . . . . .16
3/20
M48Z58, M48Z58YFigure 16.SH –4-pin SNAPHAT Housing for 120mAh Battery, Package Outline . . . . . . . . . . . . . .17
Table 14. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data . . . . . .17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 16. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 17. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
M48Z58, M48Z58Y
DESCRIPTIONThe M48Z58/Y ZEROPOWER® RAM is an 8K x 8
non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a sin-
gle die. The monolithic chip is available in two spe-
cial packages to provide a highly integrated
battery backed-up memory solution.
The M48Z58/Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT™ houses the
M48Z58/Y silicon with a long life lithium button cell
in a single package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing con-
taining the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHAT housing
is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28-lead SOIC, the battery package (e.g.,
SNAPHAT) part number is “M4Z28-BR00SH” (see
Table 16., page 18).
Table 1. Signal Names
5/20
M48Z58, M48Z58Y
Figure 6. Block Diagram
M48Z58, M48Z58Y
OPERATING MODES
The M48Z58/Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low VCC. As VCC falls be-
low battery switchover voltage (VSO), the control
circuitry connects the battery which maintains data
until valid power returns.
Table 2. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Note:1. See Table 10., page 13 for details.
READ Mode
The M48Z58/Y is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
Thus, the unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
7/20
M48Z58, M48Z58Y
Table 3. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). CL = 5pF (see Figure 11., page 11).
WRITE Mode
The M48Z58/Y is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of
W or E. The addresses must be held valid through-
out the cycle. E or W must return high for a mini-
mum of tEHAX from Chip Enable or tWHAX from
WRITE Enable prior to the initiation of another
READ or WRITE cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid fortWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
M48Z58, M48Z58Y
9/20
M48Z58, M48Z58Y
Data Retention Mode
With valid VCC applied, the M48Z58/Y operates as
a conventional BYTEWIDE™ static RAM. Should
the supply voltage decay, the RAM will automati-
cally power-fail deselect, write protecting itself
when VCC falls within the VPFD (max), VPFD (min)
window. All outputs become high impedance, and
all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z58/Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data. The internal button cell will maintain
data in the M48Z58/Y for an accumulated period of
at least 10 years when VCC is less than VSO.
As system power returns and VCC rises above
VSO, the battery is disconnected, and the power
supply is switched to external VCC. Normal RAM
operation can resume tREC after VCC exceeds
VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
M48Z58, M48Z58Y
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 5. Absolute Maximum Ratings
Note:1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds). For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds). For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
