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M48Z512AV-85PM1
4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
Not recommended for new designJune 2011 Doc ID 5146 Rev 9 1/21
M48Z512A
M48Z512AY , M48Z512AV4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
Features Integrated, ultra low power SRAM, power-fail
control circuit, and battery Conventional SRAM operation; unlimited
WRITE cycles 10 years of data retention in the absence of
power Automatic power-fail chip deselect and WRITE
protection Two WRITE protect voltages:
(VPFD = power-fail deselect voltage)
–M48Z512A: VCC = 4.75 to 5.5 V;
4.5 V ≤ VPFD ≤ 4.75 V
–M48Z512AY: VCC = 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
–M48Z512AV: VCC = 3.0 to 3.6 V;
2.8 V ≤ VPFD ≤ 3.0 V Battery internally isolated until power is applied Pin and function compatible with JEDEC
standard 512 K x 8 SRAMs PMDIP32 is an ECOPACK® package RoHS compliant Lead-free second level interconnect
DescriptionThe M48Z512A/Y/V ZEROPOWER® RAM is a
non-volatile, 4,194,304-bit static RAM organized
as 524,288 words by 8 bits. The devices combine
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module.
Contents M48Z512A, M48Z512AY, M48Z512AV2/21 Doc ID 5146 Rev 9
Contents Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M48Z512A, M48Z512AY, M48Z512AV List of tables
Doc ID 5146 Rev 9 3/21
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. PMDIP32 – 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 17
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
List of figures M48Z512A, M48Z512AY, M48Z512AV
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List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Figure 5. Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M48Z512A, M48Z512AY, M48Z512AV Device overview
Doc ID 5146 Rev 9 5/21
1 Device overview
Figure 1. Logic diagram
Table 1. Signal names
Device overview M48Z512A, M48Z512AY, M48Z512AV
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Figure 2. DIP connections
Figure 3. Block diagram
M48Z512A, M48Z512AY, M48Z512AV Operating modes
Doc ID 5146 Rev 9 7/21
2 Operating modes
The M48Z512A/Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single VCC supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low VCC. As VCC falls below the
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
The ZEROPOWER® RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
WRITEs that can be performed.
Note: See Table 10 on page 16 for details.
2.1 READ mode
The M48Z512A/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
4,194,304 locations in the static storage array. Thus, the unique address specified by the 19
address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (t AVQV ) after the last
address input signal is stable, providing that the E (chip enable) and G (output enable)
access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of chip enable access time (t ELQV ) or output enable access Time GLQV ). The state of the eight three-state data I/O signals is controlled by E and G. If the
outputs are activated before t AVQV , the data lines will be driven to an indeterminate state
until t AVQV . If the address inputs are changed while E and G remain low, output data will
remain valid for output data hold time (t AXQX ) but will go indeterminate until the next address
access.
Table 2. Operating modes X = VIH or VIL; VSO = battery backup switchover voltage.
Operating modes M48Z512A, M48Z512AY, M48Z512AV
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Figure 4. Chip enable or output enable controlled, READ mode AC waveforms WRITE enable (W) = high
Figure 5. Address controlled, READ mode AC waveforms Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
M48Z512A, M48Z512AY, M48Z512AV Operating modes
Doc ID 5146 Rev 9 9/21
2.2 WRITE mode
The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for a
minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE
cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for
tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus
contention; although, if the output bus has been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
Table 3. READ mode AC characteristics Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V,
or 3.0 to 3.6 V (except where noted). CL = 5 pF.
Operating modes M48Z512A, M48Z512AY, M48Z512AV
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Figure 6. WRITE enable controlled, WRITE AC waveforms Output enable (G) = high.
Figure 7. Chip enable controlled, WRITE AC waveforms Output enable (G) = high.
M48Z512A, M48Z512AY, M48Z512AV Operating modes
Doc ID 5146 Rev 9 11/21
2.3 Data retention mode
With valid VCC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect,
WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance,
and all inputs are treated as “don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, WRITE protection
takes place. When VCC drops below VSO, the control circuit switches power to the internal
energy source which preserves data.
The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of
VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system
power returns and VCC rises above VSO, the battery is disconnected, and the power supply
is switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to
allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
Table 4. WRITE mode AC characteristics Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V
or 3.0 to 3.6 V (except where noted). CL = 5 pF. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
