M48Z35-70MH6 ,256 Kbit (32 Kbit x 8) ZEROPOWER SRAMLogic Diagram■ SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY ..
M48Z35-70PC1 ,256 KBIT (32KB X 8) ZEROPOWER SRAMFEATURES SUMMARY
M48Z35-70MH6
256 Kbit 32Kb x8 ZEROPOWER SRAM
1/18August 1999
M48Z35
M48Z35Y256 Kbit (32Kb x8) ZEROPOWER® SRAM INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY READ CYCLE TIME EQUALS WRITE CYCLE
TIME AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48Z35: 4.50V ≤ VPFD ≤ 4.75V M48Z35Y: 4.20V ≤ VPFD ≤ 4.50V SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT® TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32K x8 SRAMs
DESCRIPTIONThe M48Z35/35Y ZEROPOWER® RAM is a 32
Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithic chip is avail-
able in two special packages to provide a highly in-
tegrated battery backed-up memory solution.
Table 1. Signal Names
M48Z35, M48Z35Y
Table 2. Absolute Maximum Ratings (1)Note:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
3/18
M48Z35, M48Z35YThe M48Z35/35Y is a non-volatile pin and function
equivalent to any JEDEC standard 32K x8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed. The 28 pin 600mil DIP
CAPHAT™ houses the M48Z35/35Y silicon with a
long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery
damage due to the high temperatures required for
device surface-mounting. The SNAPHAT housing
is keyed to prevent reverse insertion.
Table 3. Operating Modes (1)Note:1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 7 for details.
M48Z35, M48Z35YThe SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z35/35Y also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low VCC. As VCC falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODEThe M48Z35/35Y is in the Read Mode whenever
W (Write Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
WRITE MODEThe M48Z35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of tEHAX from Chip Enable or tWHAX from Write En-
able prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs tWLQZ after W falls.
Table 4. AC Measurement ConditionsNote that Output Hi-Z is defined as the point where data is no longer
driven.
5/18
M48Z35, M48Z35Y
Table 5. Capacitance (1, 2) (TA = 25 °C)
Note:1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Note:1. Outputs deselected. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics (1)(TA = 0 to 70 °C or –40 to 85 °C)
Note:1. All voltages referenced to VSS. At 25 °C.
M48Z35, M48Z35Y
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 °C or –40 to 85 °C)
Note:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200μs after VCC pass-
es VPFD (min). VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. tREC (min) = 20ms for industrial temperature grade (6) device.
7/18
M48Z35, M48Z35Y
Table 9. Read Mode AC Characteristics (TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Note:1. CL = 100pF (see Figure 4). CL = 5pF (see Figure 4).
M48Z35, M48Z35Y
Table 10. Write Mode AC Characteristics(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Note:1. CL = 5pF (see Figure 4). If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
DATA RETENTION MODEWith valid VCC applied, the M48Z35/35Y operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD(max),
VPFD(min) window. All outputs become high im-
pedance, and all inputs are treated as "don't care."
Note: A power failure during a write cycle may cor-rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD(min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48Z35/35Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data. The internal button cell will maintain
data in the M48Z35/35Y for an accumulated peri-
od of at least 10 years (at 25°C) when VCC is less
than VSO.
As system power returns and VCC rises above
VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protec-
tion continues until VCC reaches VPFD(min) plus
tREC(min). Normal RAM operation can resume
tREC after VCC exceeds VPFD(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
9/18
M48Z35, M48Z35Y
