M48Z32V-35MT1 ,3.3V, 256 Kbit (32Kbit X8) ZEROPOWER SRAMAbsolute Maximum Ratings 9DC AND AC PARAMETERS . 10Table 6. Operating and AC Measurement ..
M48Z32V-35MT1TR ,3.3V, 256 Kbit (32Kbit X8) ZEROPOWER SRAMBlock Diagram . . 4OPERATING MODES . . . . . . . 4Table 2. Operating Modes 4RE ..
M48Z35-70MH6 ,256 Kbit (32 Kbit x 8) ZEROPOWER SRAMLogic Diagram■ SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY ..
M48Z35-70PC1 ,256 KBIT (32KB X 8) ZEROPOWER SRAMFEATURES SUMMARY
M48Z32V-35MT1-M48Z32V-35MT1TR
3.3V, 256 Kbit (32Kbit X8) ZEROPOWER SRAM
1/16March 2004
M48Z32V3.3V, 256 Kbit (32 Kbit x8) ZEROPOWER® SRAM
FEATURES SUMMARY
M48Z32V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Figure 3. SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 8. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Figure 11.SOH44 – 44-lead Plastic, Hatless, Small Package Outline. . . . . . . . . . . . . . . . . . . . . . .13
Table 11. SOH44 – 44-lead Plastic, Hatless, Small Package Mechanical Data . . . . . . . . . . . . . . .13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
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M48Z32V
SUMMARY DESCRIPTIONThe M48Z32V ZEROPOWER® RAM is a 32 Kbit x
8, non-volatile static RAM that integrates power-
fail deselect circuitry and battery control logic on a
single die.
The 44-pin, 330mil SOIC provides a battery pin for
an external, user-supplied battery. This is all that
is required to fully non-volatize the SRAM.
Figure 3. SOIC ConnectionsNote: NF, Pin 7 must be tied to VSS.
M48Z32V
Figure 4. Block Diagram
OPERATING MODESThe M48Z32V also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single power supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low VCC. As VCC falls
below approximately VSO, the control circuitry con-
nects the battery which maintains data until valid
power returns.
Table 2. Operating ModesNote: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Note:1. See Table 10., page 12 for details.
5/16
M48Z32V
READ ModeThe M48Z32V is in the READ Mode whenever W
(WRITE Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 262,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
M48Z32V
WRITE ModeThe M48Z32V is in the WRITE Mode whenever W
and E are low. The start of a WRITE is referenced
from the latter occurring falling edge of W or E. A
WRITE is terminated by the earlier rising edge of
W or E. The addresses must be held valid through-
out the cycle. E or W must return high for a mini-
mum of tEHAX from Chip Enable or tWHAX from
WRITE Enable prior to the initiation of another
READ or WRITE cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid fortWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
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M48Z32V
Table 4. WRITE Mode AC CharacteristicsNote:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 3.0 to 3.6V (except where noted). CL = 5pF (see Figure 9., page 10). If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
M48Z32V
Data Retention ModeWith valid VCC applied, the M48Z32V operates as
a conventional BYTEWIDE™ static RAM. Should
the supply voltage decay, the RAM will automati-
cally power-fail deselect, write protecting itself
when VCC falls within the VPFD (max), VPFD (min)
window. All outputs become high impedance, and
all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle maycorrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
tent. At voltages below VPFD(min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z32V may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the external battery which pre-
serves data.
As system power returns and VCC rises above
VSO, the battery is disconnected, and the power
supply is switched to external VCC. Write protec-
tion continues until VCC reaches VPFD(min) plus
tREC(min). Normal RAM operation can resume
tREC after VCC exceeds VPFD(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
