M48Z30Y-100PM1 Fast Delivery |IC PHOENIX CO.,LIMITED

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M48Z35-70PC1 ,256 KBIT (32KB X 8) ZEROPOWER SRAMFEATURES SUMMARY

M48Z30Y-100PM1
CMOS 32K x 8 ZEROPOWER SRAM
Figure1. Logic Diagram
M48Z30
M48Z30Y
CMOS 32Kx8 ZEROPOWER SRAM
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
CONVENTIONALSRAM OPERATION;
UNLIMITED WRITE CYCLES YEARSof DATA RETENTIONin the
ABSENCEof POWER
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32Kx8 SRAMs
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
CHOICEof TWO WRITE PROTECT
VOLTAGES: M48Z30: 4.5V≤ VPFD≤ 4.75V M48Z30Y: 4.2V≤ VPFD≤ 4.50V
BATTERYINTERNALLY ISOLATEDUNTIL
POWERIS APPLIED
DESCRIPTION
The M48Z30/30Y32Kx8 ZEROPOWER RAMis non-volatile262,144bit Static RAM organizedas
32,768 wordsby8 bits. The device combinesan
internal lithium battery and afull CMOS SRAMina
plastic 28 pin DIP Module. The ZEROPOWER- A14 Address Inputs
DQ0- DQ7 Data Inputs/ Outputs Chip Enable Output Enable Write Enable
VCC Supply Voltage
VSS Ground
Table1. Signal Names
PMDIP28 (PM)
Module
July 1994 1/12
Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damagetothe device. Thisisa stress
rating only and functional operationofthe deviceat theseor any other conditions above those indicatedinthe operational sectionof this
specificationis notimplied. Exposuretothe absolute maximum ratings conditionsfor extended periodsof time may affect reliability.
CAUTION: Negative undershootsbelow –0.3 voltsare notallowedonanypin while inthe Battery Back-up mode.
Symbol Parameter Value Unit Ambient Operating Temperature 0to70 °C
TSTG Storage Temperature(VCC Off) –40to70 °C
TBIAS Temperature Under Bias –10to70 °C
TSLD Lead Soldering Temperaturefor10 seconds 260 °C
VIO Inputor Output Voltages –0.3to7 V
VCC Supply Voltage –0.3to7 V
Table2. Absolute Maximum Ratings
Figure2. DIP Pin Connections
RAMdirectly replaces industry standardSRAMs.It
also fits into many EPROM andEEPROM sockets,
providing the nonvolatilityof PROMs without any
requirement for special write timingor limitations the numberof writes that canbe performed.
The M48Z30/30Y hasits own Power-fail Detect
Circuit. Thecontrolcircuitry constantlymonitors the
single 5V supply foran outof tolerance condition.
When VCCis outof tolerance, the circuit write
protects the SRAM, providinga high degree ofdata
securityin the midstof unpredictable system op-
erations broughtonby low VCC.AsVCC falls below
approximately3V, the controlcircuitry connectsthe
battery which sustains data until valid power re-
turns.
READ MODE
The M48Z30/30Yisin the Read Mode whenever
W(Write Enable)is high andE (Chip Enable)islow.
The device architecture allows ripple-through ac-
cessof datafrom eightof 262,144 locationsin the
static storage array. Thus, the unique address
Mode VCC E G W DQ0-DQ7 Power
Deselect
4.75Vto 5.5V
4.5Vto 5.5V
VIH X X HighZ Standby
Write VIL XVIL DIN Active
Read VIL VIL VIH DOUT Active
Read VIL VIH VIH HighZ Active
Deselect VSOto VPFD (min) X X X HighZ CMOS Standby
Deselect ≤ VSO X X X HighZ Battery Back-up Mode
Table3. OperatingModes
Note:X=VIHorVIL
DESCRIPTION (cont’d)
2/12
M48Z30, M48Z30Y
specifiedby the 15 Address Inputs defines which
oneof the 32,768 bytesof dataistobe accessed.
Valid data will be availableat the Data I/O pins
within tAVQV (Address Access Time) after the last
address input signalis stable, providing that theE
andG (Output Enable) access times are also sat-
isfied.IftheE and Gaccess times are notmet, valid
data willbe available after the laterof Chip Enable
Access Time(tELQV) orOutput Enable Access Time
(tGLQV).
The stateof the eight three-stateData I/O signals controlled byE andG.If the outputsareactivated
before tAVQV, the data lines will be drivento an
indeterminate state until tAVQV.If the Address In-
puts are changed whileE andG remain low, output
data will remain valid for tAXQX (Output Data Hold
Time) but will go indeterminate until the next Ad-
dress Access.
WRITE MODE
TheM48Z30/30Yisin the Write Mode wheneverW
andE are active. The startofa writeis referenced
from the latter occurring falling edgeofWorE.
Figure4. AC Testing Load Circuit
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0to3V
Input and Output Timing Ref. Voltages 1.5V MEASUREMENT CONDITIONS
Note that Output Hi-Zis definedasthe point where datano longer driven.
Figure3. Block Diagram
3/12
M48Z30, M48Z30Y
Symbol Parameter Test Condition Min Max Unit
ILI(1) Input Leakage Current 0V≤ VIN≤ VCC ±1 μA
ILO(1) Output Leakage Current 0V≤ VOUT≤ VCC ±1 μA
ICC Supply Current E= VIL, Outputs open 85 mA
ICC1 Supply Current (Standby) TTL E=VIH 7mA
ICC2 Supply Current (Standby) CMOS E≥ VCC– 0.2V 4 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2.2 VCC+0.3 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High Voltage IOH= –1mA 2.4 V
Note:1. Outputsdeselected.
Table5. DC Characteristics (TA=0to 70°C; VCC= 4.75Vto 5.5Vor 4.5Vto 5.5V)
Symbol Parameter TestCondition Min Max Unit
CIN Input Capacitance VIN =0V 10 pF
CIO(3) Input/ Output Capacitance VOUT =0V 10 pF
Table4. Capacitance(1,2) (TA =25 °C,f=1 MHz)
Notes:1. Effective capacitance measured with powersupplyat5V. Sampled only,not100% tested. Outputs deselected
Symbol Parameter Min Typ Max Unit
VPFD Power-fail Deselect Voltage(M48Z30) 4.5 4.6 4.75 V
VPFD Power-fail Deselect Voltage(M48Z30Y) 4.2 4.3 4.5 V
VSO Battery Back-up Switchover Voltage 3 V
tDR(2) Data Retention Time 10 YEARS
Notes:1. Allvoltages referenced toVSS.@ 25°C
Table6. Power Down/Up Trip Points DC Characteristics(1) (TA=0to 70°C)
4/12
M48Z30, M48Z30Y
Symbol Parameter Min Max Unit(1) VPFD (max)to VPFD (min) VCC Fall Time 300 μs
tFB(2) VPFD (min)to VSO VCC Fall Time 10 μs
tWP Write Protect Time from VCC =VPFD 40 150 μs VSOto VPFD (max) VCC Rise Time 0 μs
tER E Recovery Time 40 120 ms
Notes:1. VPFD (max) toVPFD (min)fall timeof less thantF may resultin deselection/write protectionnot occurring until200μs after
VCC passes VPFD (min). VPFD (min)to VSO falltimeof less thantFB may cause corruptionof RAM data.
Table7. Power Down/Up Mode AC Characteristics (TA=0to 70°C)
Figure5. Power Down/Up Mode AC Waveforms
5/12
M48Z30, M48Z30Y
Symbol Parameter
M48Z30/ 30Y
Unit-85 -100
Min Max Min Max
tAVAV Read Cycle Time 85 100 ns
tAVQV(1) Address Validto Output Valid 85 100 ns
tELQV(1) Chip Enable Lowto Output Valid 85 100 ns
tGLQV(1) Output Enable Lowto Output Valid 45 50 ns
tELQX(2) Chip Enable Lowto Output Transition 5 5 ns
tGLQX(2) Output Enable Lowto Output Transition 5 5 ns
tEHQZ(2) Chip Enable Highto Output Hi-Z 40 40 ns
tGHQZ(2) Output Enable Highto OutputHi-Z 35 35 ns
tAXQX(1) Address Transitionto Output Transition 10 10 ns
Notes:1.CL= 100pF(see Figure4).CL= 5pF (see Figure4)
Table8. Read Mode AC Characteristics (TA=0to 70°C; VCC= 4.75Vto 5.5Vor 4.5Vto 5.5V)
Figure6. Address Controlled, Read Mode AC Waveforms
Note:E= Low,G= Low,W= High.
6/12
M48Z30, M48Z30Y

Partno	Mfg	Dc	Qty	Available	Descript
M48Z30Y-100PM1 \|M48Z30Y100PM1		N/a	3	avai	CMOS 32K x 8 ZEROPOWER SRAM