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M48Z18-100MH1-M48Z18-100PC6
64 Kbit 8Kb x 8 ZEROPOWER SRAM
M48Z08
M48Z1864 Kbit (8Kb x 8) ZEROPOWER® SRAM
March 1999 1/18
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMA TIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48Z08: 4.50V ≤ VPFD ≤ 4.75V M48Z18: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28 LEAD SOIC
and SNAPHAT® TOP (to be Ordered
Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
PIN and FUNCTION COMPATIBLE with the
DS1225 and JEDEC STANDARD 8K x 8
SRAMs
DESCRIPTIONThe M48Z08/18 ZEROPOWER® RAM is an 8K x
8 non-volatile static RAM which is pin and func-
tional compatible with the DS1225. The monolithic
chip is available in two special packages to provide
a highly integrated battery backed-up memory so-
lution.
Figure 1. Logic Diagram
Table 1. Signal Names
Notes:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 2. Absolute Maximum Ratings (1)
Note:1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Table 3. Operating Modes (1)
Figure 2A. DIP Pin Connections
Figure 2B. SOIC Pin Connections
Warning: NC = Not Connected. Warning: NC = Not Connected.2/18
M48Z08, M48Z18
Figure 4. AC Testing Load Circuit Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
Figure 3. Block DiagramThe M48Z08/18 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT houses the
M48Z08/18 silicon with a long life lithium button cell
in a single package.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to the
high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SOIC and battery packages are shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form.
DESCRIPTION (cont’d)3/18
M48Z08, M48Z18
Notes:1. Outputs deselects. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 6. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Notes:1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. Outputs deselected
Table 5. Capacitance (1, 2) (TA = 25 °C)
Note:1. All voltages referenced to VSS.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70°C)
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z08/18 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data until valid power re-
turns.
DESCRIPTION (cont’d)4/18
M48Z08, M48Z18
Notes:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 μs after
VCC passes VPFD (min). VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70°C)
Figure 5. Power Down/Up Mode AC Waveforms
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systemsmay perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/18
M48Z08, M48Z18
Notes:1. CL = 100pF (see Figure 4). CL = 30pF (see Figure 4).
Table 9. Read Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Figure 6. Read Mode AC Waveforms
Note: Write Enable (W) = High.6/18
M48Z08, M48Z18
Notes:1. CL = 30pF (see Figure 4). If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Table 10. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
READ MODEThe M48Z08/18 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 65,536 locations in the
static storage array. Thus, the unique address
specified by the 13 Address Inputs defines which
one of the 8,192 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
WRITE MODEThe M48Z08/18 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E.
A write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of tEHAX from Chip Enable or tWHAX from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs tWLQZ after W falls.
7/18
M48Z08, M48Z18
Figure 7. Write Enable Controlled, Write AC Waveforms
Figure 8. Chip Enable Controlled, Write AC Waveforms8/18
M48Z08, M48Z18
DATA RETENTION MODEWith valid VCC applied, the M48Z08/18 operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automat-
ically power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."
Note: A power failure during a write cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below VPFD(min), the user can
be assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z08/18 may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48Z08/18 for
an accumulated period of at least 11 years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches VPFD
(min) plus tREC (min). E should be kept high as VCC
rises past VPFD(min) to prevent inadvertent write
cycles prior to system stabilization. Normal RAM
operation can resume tREC after VCC exceeds
VPFD(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
SYSTEM BATTERY LIFEThe useful life of the battery in the M48Z08/18 is
expected to ultimately come to an end for one of
two reasons: either because it has been dis-
charged while providing current to the RAM in the
battery back-up mode, or because the effects of
aging render the cell useless before it can actually
be completely discharged. The two effects are
virtually unrelated, allowing discharge or Capacity
Consumption, and the effects of aging or Storage
Life, to be treated as two independent but simulta-
neous mechanisms. The earlier occurring failure
mechanism defines the battery system life of the
M48Z08/18.
Figure 9. Predicted Battery Storage Life versus Temperature9/18
M48Z08, M48Z18
