M48Z129V-85PM1 Fast Delivery |IC PHOENIX CO.,LIMITED

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M48Z129V-85PM1
1 MBIT (128KB X 8) ZEROPOWER SRAM
1/17April 2003
M48Z129Y*
M48Z129V
5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER® SRAM
* Contact Local Sales Office
FEATURES SUMMARY INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER MICROPROCESSOR POWER-ON RESET
(RESET VALID EVEN DURING BATTERY
BACK-UP MODE) BATTERY LOW PIN - PROVIDES WARNING
OF BATTERY END-OF-LIFE AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48Z129Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V M48Z129V: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
M48Z129Y*, M48Z129V
2/17
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 6. Address Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms. . . . . . . . . . . . . .7
Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 8. WRITE Enable Controlled, WRITE Mode AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 9. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 8. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 10. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3/17
M48Z129Y*, M48Z129V
SUMMARY DESCRIPTION
The M48Z129Y/V ZEROPOWER® SRAM is a
1,048,576 bit non-volatile static RAM organized as
131,072 words by 8 bits. The device combines an
internal lithium battery, a CMOS SRAM and a con-
trol circuit in a plastic 32-pin DIP Module. The
M48Z129Y/V directly replaces industry standard
128K x 8 SRAM. It also provides the non-volatility
of FLASH without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. Table 1. Signal Names
Figure 3. DIP Connections
M48Z129Y*, M48Z129V
4/17
Figure 4. Block Diagram
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Note:1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
5/17
M48Z129Y*, M48Z129V
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Note: Output Hi-Z is defined as the point where data is no longer driven.
Table 4. Capacitance
Note:1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. At 25°C, f = 1MHz. Outputs deselected.
M48Z129Y*, M48Z129V
6/17
Table 5. DC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). Outputs deselected.
OPERATION MODES
The M48Z129Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing data security in
the midst of unpredictable system operation. As
VCC falls, the control circuitry automatically switch-
es to the battery, maintaining data until valid power
is restored.
Table 6. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 10, page 12 for details.
7/17
M48Z129Y*, M48Z129V
READ Mode
The M48Z129Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 ad-
dress inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
Figure 6. Address Controlled, READ Mode AC Waveforms
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
M48Z129Y*, M48Z129V
8/17
Table 7. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). CL = 5pF (see Figure 5, page 5).
9/17
M48Z129Y*, M48Z129V
WRITE Mode
The M48Z129Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are ac-
tive. The start of a WRITE is referenced from the
latter occurring falling edge of W or E. A WRITE is
terminated by the earlier rising edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for a minimum of
tEHAX from Chip Enable or tWHAX from WRITE En-
able prior to the initiation of another READ or
WRITE cycle. Data-in must be valid tDVWH prior to
the end of WRITE and remain valid for tWHDX af-
terward. G should be kept high during WRITE cy-
cles to avoid bus contention; although, if the output
bus has been activated by a low on E and G a low
on W will disable the outputs tWLQZ after W falls.

Partno	Mfg	Dc	Qty	Available	Descript
M48Z129V-85PM1 \|M48Z129V85PM1	ST	N/a	50	avai	1 MBIT (128KB X 8) ZEROPOWER SRAM