M48Z128-120PM1-M48Z128Y-120PM1 Fast Delivery |IC PHOENIX CO.,LIMITED

M48Z128-120PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMM48Z128M48Z128Y1 Mbit (128Kb x8) ZEROPOWER SRAMn INTEGRATED LOW POWER SRAM,POWER-FAIL CONTROL CIRC ..
M48Z128-70PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . . . . . . . 12DC AND AC PARAMETERS . 12Table 7. Operating and ..
M48Z128Y-120PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMAbsolute Maximum Ratings” may cause permanent damage to the device. This is a stressrating only and ..
M48Z128Y-70PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. 32-pin PMDIP ModulePOWER-FAIL CONTROL ..
M48Z128Y-85PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMBlock Diagram . . 5Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution . ..
M48Z129V-85PM1 ,1 MBIT (128KB X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . 4DC AND AC PARAMETERS . . 5Table 3. Operating and AC Measurem ..
M61545AFP , Serial Data Control Dual Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M616Z08-20MH3 ,128 Kbit (8 Kbit X 16) SRAM with Output EnableLogic Diagram . . 1Table 1. Signal Names . . 1DESCRIPTION . . . . 4Figure 3. ..
M616Z08-20MH3TR ,128 Kbit (8 Kbit X 16) SRAM with Output EnableAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 7. DC and AC Meas ..
M62003FP , LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES

M48Z128-120PM1-M48Z128Y-120PM1
1 Mbit 128Kb x8 ZEROPOWER SRAM
M48Z128
M48Z128Y Mbit (128Kb x8) ZEROPOWER SRAM INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES 10 YEARSof DATA RETENTIONin the
ABSENCEof POWER AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD= Power-fail Deselect Voltage): M48Z128: 4.50V≤ VPFD≤ 4.75V M48Z128Y: 4.20V≤ VPFD≤ 4.50V BATTERY INTERNALLY ISOLATED UNTIL
POWERIS APPLIED PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 128Kx8 SRAMs SURFACE MOUNT CHIP SET PACKAGING
INCLUDESa 28-PIN SOIC anda 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY) SOIC PACKAGE PROVIDES DIRECT
CONNECTIONfora SNAPHAT TOP WHICH
CONTAINS the BATTERY SNAPHAT HOUSING (BATTERY)IS
REPLACEABLE
Figure1. Logic Diagram
AI01194
A0-A16
DQ0-DQ7CC
M48Z128
M48Z128Y
VSS
Table1. Signal Names
A0-A16 Address Inputs
DQ0-DQ7 Data Inputs/ Outputs Chip Enable Output Enable Write Enable
VCC Supply Voltage
VSS Ground Not Connected Internally
TSOP32x 20mm) SOH28
Surface Mount Chip Set Solution (CS)
SNAPHAT (SH)
Battery
PMDIP32 (PM)
Module
M48Z128, M48Z128Y
Figure2. DIP Connections
DQ0
A13
A10
DQ7
A15
A11
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6
A16 VCC
AI01195
M48Z128
M48Z128Y
A12
A143
Table2. Absolute Maximum Ratings(1)
Note:1. Stresses greater than those listed under ”Absolute Maximum Ratings” maycause permanent damageto thedevice. Thisisa stress
rating onlyand functional operationofthe deviceat theseorany other conditions above those indicatedinthe operational section this specificationisnot implied. Exposuretothe absolute maximum rating conditionsfor extended periodsof time may affect
reliability. Soldering temperaturenotto exceed 260°Cfor10 seconds (total thermal budgetnotto exceed 150°Cfor longerthan30 seconds).
CAUTION: Negative undershoots below –0.3Varenot allowedonanypin whileinthe Battery Back-up mode.
Table3. Operating Modes
Note:1.X=VIHor VIL;VSO= Battery Back-up Switchover Voltage.
Symbol Parameter Value Unit Ambient Operating Temperature 0to70 °C
TSTG Storage Temperature (VCC Off) –40to70 °C
TBIAS Temperature Under Bias –10to70 °C
TSLD(2) Lead Solder Temperaturefor10 seconds 260 °C
VIO Inputor Output Voltages –0.3to7 V
VCC Supply Voltage –0.3to7 V
Mode VCC E G W DQ0-DQ7 Power
Deselect
4.75Vto 5.5V
4.5Vto 5.5V
VIH X X HighZ Standby
Write VIL X VIL DIN Active
Read VIL VIL VIH DOUT Active
Read VIL VIH VIH HighZ Active
Deselect VSOto VPFD(min) X X X HighZ CMOS Standby
Deselect ≤ VSO X X X HighZ Battery Back-up Mode
DESCRIPTION
The M48Z128/128Y ZEROPOWER RAMisa
128 Kbitx8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logicona single die. The monolithic chipis avail-
ablein two special packagesto provide ahighlyin-
tegrated battery backed-up memory solution.
The M48Z128/128Yisa non-volatile pin and func-
tion equivalentto any JEDEC standard 128K x8
SRAM.It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility PROMs without any requirement for special
write timingor limitationson the numberof writes
that can be performed. The 32 pin 600mil DIP
Module houses the M48Z128/128Y silicon witha
long life lithium button cellina single package.
For surface mountenvironments ST providesa Chip
Set solution consistingofa 28 pin 330mil SOIC
NVRAM Supervisor (M40Z300) anda 32pin TSOPx 20mm) LPSRAM (M68Z128) packages.
The 28 pin 330mil SOIC provides sockets with
gold plated contactsat both ends for direct con-
nectiontoa separate SNAPHAT housing contain-
ing the battery.
M48Z128, M48Z128Y
Figure3. Block Diagram
AI01196
INTERNAL
BATTERY
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072x8
SRAM ARRAY
A0-A16
DQ0-DQ7
POWER
The unique design allows the SNAPHAT battery
packageto be mountedon topof the SOIC pack-
age after the completionof the surface mount pro-
cess. Insertionof the SNAPHAT housing after
reflow prevents potential battery damage dueto
the high temperatures requiredfor device surface-
mounting. The SNAPHAT housingis keyedto pre-
vent reverse insertion.
The SNAPHAT battery packageis shipped sepa-
ratelyin plastic anti-static tubesorin Tape& Reel
form. The part numberis ”M4Z28-BRxxSH1”.
The M48Z128/128Y also hasits own Power-fail
Detect circuit. Thecontrol circuitry constantly mon-
itors the single 5V supply foran outof tolerance
condition. When VCCis outof tolerance, the circuit
write protects the SRAM, providinga high degree data securityin the midstof unpredictable sys-
tem operation broughtonby low VCC.As VCC falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODE
The M48Z128/128Yisin the Read Mode whenev-W (Write Enable)is high andE (Chip Enable)is
low. The device architecture allows ripple-through
accessof data from eightof 1,048,576 locationsin
the static storage array. Thus, the unique address
specifiedby the17 Address Inputs defines which
oneof the 131,072 bytesof dataistobe accessed.
Valid data will be availableat the Data I/O pins
within Address Access time (tAVQV) after the last
address input signalis stable, providing that theE
andG (Output Enable) access times are also sat-
isfied.If the EandG access times are notmet, val- data will be available after the laterof Chip
Enable Access time (tELQV)or Output Enable Ac-
cess Time (tGLQV). The stateof the eight three-
state Data I/O signalsis controlledbyE andG.If
the outputs are activated before tAVQV, the data
lines willbe driventoan indeterminate state until
tAVQV.If the Address Inputs are changed whileE
andG remain low, output data will remain validfor
Output Data Hold time (tAXQX) but willgo indeter-
minate until the next Address Access.
M48Z128, M48Z128Y
Table4. AC Measurement Conditions
Notethat Output Hi-Zis definedas thepoint where dataisno longer
driven.
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0to3V
Input and Output Timing Ref. Voltages 1.5V
Figure4. Hardware Hookup for SMT Chip Set(1)
Note:1.Forpin connections, see individual data sheetsfor M40Z300 and M68Z128at . Connect THSpin toVOUTif 4.2V ≤ VPFD≤ 4.5V (M48Z128Y)or connect THSpinto VSSif 4.5V≤ VPFD≤ 4.75V (M48Z128). SNAPHAT ordered separately.
AI03625 CON
VSS
VOUTTHS(2)
M40Z300
E2CON CON CON
VSS
VCC
M68Z128
A0-A16
DQ0-DQ7
SNAPHAT
BATTERY(3)
RST
Figure5. AC Testing Load Circuit
AI01030
OUTL= 100pFor 5pF L includesJIG capacitance
1.9kΩ
DEVICE
UNDER
TEST
1kΩ
M48Z128, M48Z128Y
Table5. Capacitance(1,2)
(TA =25 °C,f= 1MHz)
Note:1. Effective capacitance measured with power supplyat5V. Sampled only,not 100% tested. Outputs deselected.
Table6. DC Characteristics
(TA=0to70 °C; VCC= 4.75Vto 5.5Vor 4.5Vto 5.5V)
Note:1. Outputs deselected.
Table7. Power Down/Up Trip Points DC Characteristics(1)
(TA=0to70 °C)
Note:1.All voltages referencedto VSS.At25°C.
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 10 pF
CIO(3) Input/ OutputCapacitance VOUT =0V 10 pF
Symbol Parameter Test Condition Min Max Unit
ILI(1) Input Leakage Current 0V≤ VIN≤ VCC ±1 μA
ILO(1) Output Leakage Current 0V≤ VOUT≤ VCC ±1 μA
ICC Supply Current E= VIL, Outputs open 105 mA
ICC1 Supply Current (Standby) TTL E=VIH 7mA
ICC2 Supply Current (Standby) CMOS E≥ VCC– 0.2V 4 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2.2 VCC+0.3 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High Voltage IOH= –1mA 2.4 V
Symbol Parameter Min Typ Max Unit
VPFD Power-fail Deselect Voltage
M48Z128 4.5 4.6 4.75 V
M48Z128Y 4.2 4.3 4.5 V
VSO Battery Back-up Switchover Voltage 3 V
tDR(2) Data Retention Time 10 YEARS
M48Z128, M48Z128Y
Table8. Power Down/Up AC Characteristics
(TA=0to70 °C)
Note:1. VPFD (max)to VPFD (min) falltimeof less thantF may result indeselection/write protectionnot occurring until 200μs after VCC pass- VPFD (min). VPFD (min)to VSOfall timeof less thantFB may cause corruptionof RAM data.
Symbol Parameter Min Max Unit(1) VPFD (max)to VPFD (min) VCC Fall Time 300 μs
tFB(2) VPFD (min)to VSO VCC Fall Time 10 μs
tWP Write Protect Time from VCC =VPFD 40 150 μs VSOto VPFD (max) VCC Rise Time 0 μs
tER E Recovery Time 40 120 ms
Figure6. Power Down/Up Mode AC Waveforms
AI01031
VCC
(PER CONTROLINPUT)
OUTPUTS
DON’T CARE
HIGH-Z
tFB
tWP
tDR
VALID VALID
(PER CONTROLINPUT)
RECOGNIZEDRECOGNIZED
VPFD (max)
VPFD (min)
VSO
tER
M48Z128, M48Z128Y
Figure7. Address Controlled, Read Mode AC Waveforms
Note: Chip Enable(E) and Output Enable(G)= Low, Write Enable(W)= High.
AI01078
tAVAV
tAVQV tAXQX
A0-A16
DQ0-DQ7
VALID
DATA VALID
Table9. Read Mode AC Characteristics
(TA=0to70 °C; VCC= 4.75Vto 5.5Vor 4.5Vto 5.5V)
Note:1.CL= 100pF.CL= 5pF.
Symbol Parameter
M48Z128/M48Z128Y
Unit-70 -85 -120
Min Max Min Max Min Max
tAVAV Read Cycle Time 70 85 120 ns
tAVQV(1) Address Validto Output Valid 70 85 120 ns
tELQV(1) Chip Enable Lowto Output Valid 70 85 120 ns
tGLQV(1) Output Enable Lowto Output Valid 35 45 60 ns
tELQX(2) Chip Enable Lowto Output Transition 5 5 5 ns
tGLQX(2) Output Enable Lowto Output Transition 3 3 3 ns
tEHQZ(2) Chip Enable Highto Output Hi-Z 30 35 45 ns
tGHQZ(2) Output Enable Highto Output Hi-Z 20 25 35 ns
tAXQX(1) Address Transitionto Output Transition 5 5 10 ns
M48Z128, M48Z128Y
Figure8. Chip Enableor Output Enable Controlled, Read Mode AC Waveforms
Note: Write Enable (W)= High.
AI01197
tAVAV
tAVQV tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
DQ0-DQ7
VALID
WRITE MODE
The M48Z128/128Yisin the Write Mode whenev-W andE are active. The startofa writeis refer-
enced from the latter occurring falling edgeofWorA writeis terminatedby the earlier rising edgeWorE.
The addresses mustbe held valid throughout the
cycle.EorW must return high for minimumoftE-
HAX fromEor tWHAX fromW priorto the initiation another reador write cycle. Data-in mustbe val- tDVWH priorto the endof write and remain valid
for tWHDXor tEHDX afterward.G should be kept
high during write cyclesto avoid bus contention;
although,if the output bus has been activatedbya
lowonE andG,a lowonW will disable the outputs
tWLQZ afterW falls.
DATA RETENTION MODE
With valid VCC applied, the M48Z128/128Y oper-
atesasa conventional BYTEWIDETM static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protectingit-
self tWP after VCC falls below VPFD. All outputs
become high impedance, andall inputs are treated ”don’t care.” power fail detection occurs duringa valid ac-
cess, the memory cycle continuesto completion.If
the memory cycle failsto terminate within the time
tWP, write protection takes place. When VCC drops
below VSO, the control circuit switches powerto
the internal energy source which preserves data.
The internal coin cell will maintain datain the
M48Z128/128Y after the initial applicationof VCC
for an accumulated periodofat least 10 years
when VCCis less than VSO. As system power re-
turns and VCC rises above VSO, the batteryis dis-
connected, and the power supplyis switchedto
external VCC. Write protection continuesfor tERaf-
ter VCC reaches VPFDto allow for processor stabi-
lization. After tER, normal RAM operation can
resume.
For more informationon Battery Storage Life refer the Application Note AN1012.
M48Z128, M48Z128Y
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
ICC transients, including those producedby output
switching, can produce voltage fluctuations, re-
sultingin spikeson the VCC bus. These transients
canbe reducedif capacitors are usedto store en-
ergy, which stabilizes the VCC bus. The energy
storedin the bypass capacitors willbe releasedas
low going spikes are generatedor energy willbe
absorbed when overshoots occur.A ceramic by-
pass capacitor valueof 0.1μF (as shownin Figureis recommendedin orderto provide the needed
filtering. additionto transients that are causedby normal
SRAM operation, power cycling can generate neg-
ative voltage spikeson VCC that driveitto values
below VSSbyas muchas one Volt. These nega-
tive spikes can cause data corruptionin the SRAM
whilein battery backup mode. To protect from
these voltage spikes,itis recommendedto con-
necta schottky diode from VCCto VSS (cathode
connectedto VCC, anodeto VSS). Schottky diode
1N5817is recommended for through hole and
MBRS120T3is recommended for surface mount.
Figure9. Supply Voltage Protection
AI02169
VCC
0.1μF DEVICECCSS
Table 10. Write Mode AC Characteristics
(TA=0to70 °C; VCC= 4.75Vto 5.5Vor 4.5Vto 5.5V)
Note:1.CL= 5pF.IfE goeslow simultaneously withW goinglow afterW going low,the outputs remaininthe high impedance state.
Symbol Parameter
M48Z128/M48Z128Y
Unit-70 -85 -120
Min Max Min Max Min Max
tAVAV Write Cycle Time 70 85 120 ns
tAVWL Address Validto Write Enable Low 0 0 0 ns
tAVEL Address Validto Chip Enable Low 0 0 0 ns
tWLWH Write Enable Pulse Width 55 65 85 ns
tELEH Chip Enable Lowto Chip Enable High 55 75 100 ns
tWHAX Write Enable Highto Address Transition 5 5 5 ns
tEHAX Chip Enable Highto Address Transition 15 15 15 ns
tDVWH Input Validto Write Enable High 30 35 45 ns
tDVEH Input Validto Chip Enable High 30 35 45 ns
tWHDX Write Enable Highto Input Transition 0 0 0 ns
tEHDX Chip Enable Highto Input Transition 10 10 10 ns
tWLQZ(1,2) Write Enable Lowto Output Hi-Z 25 30 40 ns
tAVWH Address Validto Write Enable High 65 75 100 ns
tAVEH Address Validto Chip Enable High 65 75 100 ns
tWHQX(1,2) Write Enable Highto Output Transition 5 5 5 ns

Partno	Mfg	Dc	Qty	Available	Descript
M48Z128-120PM1 \|M48Z128120PM1	ST	N/a	73	avai	1 MBIT (128KB X 8) ZEROPOWER SRAM
M48Z128Y-120PM1 \|M48Z128Y120PM1	ST	N/a	1	avai	1 MBIT (128KB X 8) ZEROPOWER SRAM