M48Z02-150PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMTABLE OF CONTENTSSUMMARY DESCRIPTION . . . 3Figure 2.
M48Z02-150PC1. ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram Table 1. Signal NamesA0-A10 Address InputsVCCDQ0-DQ7 Data Inputs / Outputs11 8E Chip ..
M48Z02-150PC6 ,CMOS 2K x 8 zeropower SRAM, 150nsBlock DiagramA0-A10LITHIUMDQ0-DQ7CELLPOWER2K x 8SRAM ARRAYVOLTAGE SENSEANDESWITCHING VPFDCIRCUITRYW ..
M48Z02-200PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMLogic Diagram . . 3Table 1. Signal Names . . . 3Figure 3. DIP Connections 3Fig ..
M48Z02-200PC1 ,16 KBIT (2KB X 8) ZEROPOWER SRAMBlock Diagram . . 4MAXIMUM RATING . 4Table 2.
M48Z02-200PC6 ,CMOS 2K x 8 zeropower SRAM, 200nsAbsolute Maximum Ratings . 4DC AND AC PARAMETERS . . 5Table 3. Operating and AC Measurem ..
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61523FP , Electronic Volume with Scf Type Tone Control To 6 Speakers
M61538FP , 6-Channel Electronic Volume
M61538FP , 6-Channel Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M61545AFP , Serial Data Control Dual Electronic Volume
M48Z02-150PC1-M48Z02-150PC1.-M48Z02-150PC6-M48Z02-200PC1-M48Z02-70PC1-M48Z12-150PC1-M48Z12-200PC1-M48Z12-70PC1
16 KBIT (2KB X 8) ZEROPOWER SRAM
1/16April 2003
M48Z02
M48Z125V, 16 Kbit (2Kb x 8) ZEROPOWER® SRAM
FEATURES SUMMARY INTEGRATED, ULTRA LOW POWER SRAM
and POWER-FAIL CONTROL CIRCUIT UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE
TIME AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage): M48Z02: VCC = 4.75 to 5.5V;
4.5V ≤ VPFD ≤ 4.75V M48Z12: VCC = 4.5 to 5.5V;
4.2V ≤ VPFD ≤ 4.5V SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2K x 8 SRAMs
M48Z02, M48Z122/16
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 6. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 7. WRITE Enable Controlled, WRITE AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 8. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 8. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 9. Checking the BOK Flag Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 10. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 11. Crystal Accuracy Across Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 12. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/16
M48Z02, M48Z12
SUMMARY DESCRIPTIONThe M48Z02/12 ZEROPOWER® RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220.
A special 24-pin, 600mil DIP CAPHAT™ package
houses the M48Z02/12 silicon with a long life lithi-
um button cell to form a highly integrated battery
backed-up memory solution.
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data functionality for
an accumulated time period of at least 10 years in
the absence of power over commercial operating
temperature range.
The M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
Table 1. Signal Names
M48Z02, M48Z12
4/16
Figure 4. Block Diagram
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Note:1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
5/16
M48Z02, M48Z12
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Note: Output Hi-Z is defined as the point where data is no longer driven.
Table 4. Capacitance
Note:1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. At 25°C, f = 1MHz. Outputs deselected.
M48Z02, M48Z12
6/16
Table 5. DC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). Outputs deselected. Negative spikes of –1V allowed for up to 10ns once per Cycle.
OPERATION MODES
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low VCC. As VCC falls be-
low approximately 3V, the control circuitry con-
nects the battery which maintains data operation
until valid power returns.
Table 6. Operating Modes
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 10, page 11 for details.
7/16
M48Z02, M48Z12
READ Mode
The M48Z02/12 is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
Figure 6. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
Table 7. READ Mode AC Characteristics
Note:1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
M48Z02, M48Z12
8/16
WRITE Mode
The M48Z02/12 is in the WRITE Mode whenever
W and E are active. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid tD-
VWH prior to the end of WRITE and remain valid fortWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
Figure 7. WRITE Enable Controlled, WRITE AC Waveform
Figure 8. Chip Enable Controlled, WRITE AC Waveforms
